Issue No. 06 - November/December (2003 vol. 20)
Juha Plosila , University of Turku
Tiberiu Seceleanu , University of Turku
Pasi Liljeberg , University of Turku
<p><it>Editor's note:</it>The authors propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure.</p><p><it>—Fabrizio Lombardi, Northeastern University</it></p>
P. Liljeberg, T. Seceleanu and J. Plosila, "Implementation of a Self-Timed Segmented Bus," in IEEE Design & Test of Computers, vol. 20, no. , pp. 44-50, 2003.