Issue No. 06 - November/December (2003 vol. 20)
Satish K. Bandapati , University of Missouri-Rolla
Scott C. Smith , University of Missouri-Rolla
Minsu Choi , University of Missouri-Rolla
<p><it>Editor's note:</it> This article presents various 4-bit × 4-bit unsigned multipliers designed using the delay-insensitive null convention logic paradigm. Simulation results show a large variance in circuit performance in terms of power, area, and speed. This study will serve as a good reference for designers who wish to accomplish high-performance, low-power implementations of clockless digital VLSI circuits.</p><p><it>—Yong-Bin Kim, Northeastern University</it></p>
M. Choi, S. C. Smith and S. K. Bandapati, "Design and Characterization of Null Convention Self-Timed Multipliers," in IEEE Design & Test of Computers, vol. 20, no. , pp. 26-36, 2003.