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Issue No. 05 - September/October (2003 vol. 20)
ISSN: 0740-7475
pp: 58-66
Nagesh Tamarapalli , Mentor Graphics
Jerzy Tyszer , Poznan University of Technology
Mark Kassab , Mentor Graphics
Nilanjan Mukherjee , Mentor Graphics
Jun Qian , Cisco Systems
Janusz Rajski , Mentor Graphics
<p><div><em>Editor's note: </em></div>You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques can provide high fault coverage with low test times.<div><em>—Rob Aitken, Artisan Components</em></div></p>
Nagesh Tamarapalli, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Jun Qian, Janusz Rajski, "Embedded Deterministic Test for Low-Cost Manufacturing", IEEE Design & Test of Computers, vol. 20, no. , pp. 58-66, September/October 2003, doi:10.1109/MDT.2003.1232257
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