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Issue No. 05 - September/October (2003 vol. 20)
ISSN: 0740-7475
pp: 41-45
Rohit Kapur , Synopsys
Bruce D. Cory , nVidia
Bill Underwood , Synopsys
ABSTRACT
<p><div><em>Editor's note: </em></div>What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula to relate structural critical-path testing frequency to system-operation frequency. They demonstrate that there can be a high correlation between frequencies resulting from structural testing and those resulting from functional testing.<div><em>—Li-C. Wang, University of California, Santa Barbara</em></div></p>
INDEX TERMS
CITATION
Rohit Kapur, Bruce D. Cory, Bill Underwood, "Speed Binning with Path Delay Test in 150-nm Technology", IEEE Design & Test of Computers, vol. 20, no. , pp. 41-45, September/October 2003, doi:10.1109/MDT.2003.1232255
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