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Issue No. 05 - September/October (2003 vol. 20)
ISSN: 0740-7475
pp: 17-25
Janusz Rajski , Mentor Graphics
Ron Press , Mentor Graphics
Nagesh Tamarapalli , Mentor Graphics
Bruce Swanson , Mentor Graphics
Thomas Rinderknecht , Mentor Graphics
Paul Reuter , Mentor Graphics
Xijiang Lin , Mentor Graphics
<p><div><em>Editor's note: </em></div>At-speed scan testing has demonstrated many successes in industry. One key feature is its ability to use on-chip clock for accurate timing in the application of test vectors in a tester. The authors describe new strategies where at-speed scan tests can be applied with internal PLLs. They present techniques for optimizing ATPG across multiple clock domains and propose methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.<div><em>—Li-C. Wang, University of California, Santa Barbara</em></div></p>
Janusz Rajski, Ron Press, Nagesh Tamarapalli, Bruce Swanson, Thomas Rinderknecht, Paul Reuter, Xijiang Lin, "High-Frequency, At-Speed Scan Testing", IEEE Design & Test of Computers, vol. 20, no. , pp. 17-25, September/October 2003, doi:10.1109/MDT.2003.1232252
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