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Issue No. 04 - July/August (2003 vol. 20)
ISSN: 0740-7475
pp: 32-39
Alfredo Benso , Politecnico di Torino
Stefano Di Carlo , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Yervant Zorian , Virage Logic
<p>HD2BIST?a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems?maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes flexibility for chip designers planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system.</p>

Y. Zorian, P. Prinetto, A. Benso and S. Di Carlo, "A Hierarchical Infrastructure for SoC Test Management," in IEEE Design & Test of Computers, vol. 20, no. , pp. 32-39, 2003.
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