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Issue No.04 - July/August (2003 vol.20)
pp: 32-39
Alfredo Benso , Politecnico di Torino
Stefano Di Carlo , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Yervant Zorian , Virage Logic
<p>HD2BIST?a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems?maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes flexibility for chip designers planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system.</p>
Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian, "A Hierarchical Infrastructure for SoC Test Management", IEEE Design & Test of Computers, vol.20, no. 4, pp. 32-39, July/August 2003, doi:10.1109/MDT.2003.1214350
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