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Issue No. 03 - May/June (2003 vol. 20)
ISSN: 0740-7475
pp: 40-47
David Ayers , Intel
Vivek Tiwari , Intel
<p><em>Editor?s note:</em><div>This article takes a high-level view of the power-grid noise problem as it relates to the microarchitectural definition of an IC. Through an astonishing set of simulations, the authors relate the noise problem to the details of the circuit and clocking implementation, giving insight into possible methods to reduce such noise.</div><div>--Sani R. Nassif, IBM Austin Research Laboratory</div></p>

E. Grochowski, D. Ayers and V. Tiwari, "Microarchitectural dI/dt Control," in IEEE Design & Test of Computers, vol. 20, no. , pp. 40-47, 2003.
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