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TABLE OF CONTENTS
Issue No. 02 - March/April (vol. 20)
ISSN: 0740-7475

Guest editors' introduction: board test (PDF)

M. Lobetti-Bodoni , Siemens Mobile Communications
pp. 5-7

Minimizing pattern count for interconnect test under a ground bounce constraint (Abstract)

E.J. Marinissen , Philips Res. Labs., Eindhoven, Netherlands
B. Vermeulen , Philips Res. Labs., Eindhoven, Netherlands
H. Hollmann , Philips Res. Labs., Eindhoven, Netherlands
pp. 8-18

Embedded boundary scan (Abstract)

B.G. Van Treuren , Test Solutions Group, Lucent Technol., Holmdel, NJ, USA
J.M. Miranda , Test Solutions Group, Lucent Technol., Holmdel, NJ, USA
pp. 20-25

Electromagnetic signatures as a tool for connectionless test (Abstract)

M. Salamati , Electron. Production Eng. Res. Group, Orebro Univ., Sweden
D. Stranneby , Electron. Production Eng. Res. Group, Orebro Univ., Sweden
pp. 26-30

Extending IEEE Std. 1149.4 analog boundary modules to enhance mixed-signal test (Abstract)

U. Kac , Jozef Stefan Inst., Ljubljana, Slovenia
F. Novak , Jozef Stefan Inst., Ljubljana, Slovenia
pp. 32-39

Fast fault simulation for nonlinear analog circuits (Abstract)

N. Engin , Philips Res. Labs., Eindhoven, Netherlands
pp. 40-47

A design-for-verification technique for functional pattern reduction (Abstract)

Chien-Nan Jimmy Liu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
I-Ling Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 48-55

Compilation for FPGA-based reconfigurable hardware (Abstract)

J.M.P. Cardoso , Fac. of Sci. & Technol., Univ. of Algarve, Faro, Portugal
pp. 65-75
EIC Message
Features

Guest Editors' Introduction: Board Test (HTML)

Monica Lobetti-Bodoni , Siemens Mobile Communications
R.G.(Ben) Bennetts , Bennetts Associates
pp. 5-7

Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint (Abstract)

Erik Jan Marinissen , Philips Research Laboratories
Bart Vermeulen , Philips Research Laboratories
Henk Hollmann , Philips Research Laboratories
R.G.(Ben) Bennetts , Bennetts Associates
pp. 8-18

Embedded Boundary Scan (Abstract)

Bradford G. Van Treuren , Lucent Technologies
Jose M. Miranda , Lucent Technologies
pp. 20-25

Electromagnetic Signatures as a Tool for Connectionless Test (Abstract)

Mahnaz Salamati , Orebro University
Dag Stranneby , Orebro University
pp. 26-30

Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test (Abstract)

Uros Kac , Jozef Stefan Institute
Franc Novak , Jozef Stefan Institute
Pascal Nouet , LIRMM
pp. 32-39
Special Features

Fast Fault Simulation for Nonlinear Analog Circuits (Abstract)

Nur Engin , Philips Research Laboratories
Hans G. Kerkhoff , MESA+ Research Institute
pp. 40-47

A Design-for-Verification Technique for Functional Pattern Reduction (Abstract)

Chien-Nan Jimmy Liu , National Chiao Tung University
I-Ling Chen , National Chiao Tung University
Jing-Yang Jou , National Chiao Tung University
pp. 48-55

Compilation for FPGA-Based Reconfigurable Hardware (Abstract)

Jo?o M. P. Cardoso , University of Algarve
Hor?cio C. Neto , Technical University of Lisbon
pp. 65-75
Round Table

Test Data Compression (Abstract)

pp. 76-87
Conference Reports

Conference Reports (Abstract)

pp. 88-89
Panel Summaries

ITC 2002 Panels: Part 2 (Abstract)

pp. 90-91
Newsletters

DATC Newsletter (Abstract)

pp. 93

TTTC Newsletter (Abstract)

pp. 94-95
The Last Byte

Testing for what? (Abstract)

Kenneth P. Parker , Agilent Technologies
pp. 96
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