Issue No. 02 - March/April (2003 vol. 20)
Jo?o M. P. Cardoso , University of Algarve
Hor?cio C. Neto , Technical University of Lisbon
<p>These techniques for compiling software programs into reconfigurable hardware offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems. The Java-based compiler presented in this article uses intermediate graph representations to embody parallelism at various levels.</p>
J. M. Cardoso and H. C. Neto, "Compilation for FPGA-Based Reconfigurable Hardware," in IEEE Design & Test of Computers, vol. 20, no. , pp. 65-75, 2003.