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Issue No. 02 - March/April (2003 vol. 20)
ISSN: 0740-7475
pp: 40-47
Nur Engin , Philips Research Laboratories
Hans G. Kerkhoff , MESA+ Research Institute
<p>A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.</p>

H. G. Kerkhoff and N. Engin, "Fast Fault Simulation for Nonlinear Analog Circuits," in IEEE Design & Test of Computers, vol. 20, no. , pp. 40-47, 2003.
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