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2002 IEEE Design & Test of Computers Annual Index, Volume 19

Pages: pp. 110-119


This index includes all items appearing in this periodical during 2002 that are considered to have archival value. (The item title is listed only under the primary author entry in the author index.)

AUTHOR INDEXAAitken, R.,and D. Wheater, "Guest Editors' Introduction: Stressing the Fundamentals," Special ITC Section, Sept.-Oct. 02, pp. 5-7.Aktouf, C.,"A Complete Strategy for Testing an On-Chip Multiprocessor Architecture," Jan.-Feb. 02, pp. 18-28.Aragonès, X.,et al.,"Noise Generation and Coupling Mechanisms in Deep-Submicron ICs," Sept.-Oct. 02, pp. 27-35.Ashenden, P.J.,"Verilog and Other Standards," Standards, Jan.-Feb. 02, pp. 84-85.Ashenden, P.J.,"The IEEE Standards Process," Standards, Mar.-Apr. 02, pp. 72-73.Ashenden, P.J.,"What Makes a Good Standard?" Standards, May-June 02, p. 114.Azaïs, F.,Renovell, M., Nov.-Dec. 02, pp. 83-89.BBarnhart, C.,et al., "Extending OPMISR beyond 10x Scan Test Efficiency," Sept.-Oct. 02, pp. 65-73.Bayraktaroglu, I.,and A. Orailoglu, "Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST," Jan.-Feb. 02, pp. 42-53.Benini, L.,Dalpasso, M., Sept.-Oct. 02, pp. 92-104.Benso, A.,S. Chiusano, and P. Prinetto, "DFT and BIST of a Multichip Module for High-Energy Physics Experiments," May-June 02, pp. 94-105.Bensoudane, E.,Paulin, P., Nov.-Dec. 02, pp. 17-26.Bertrand, Y.,Renovell, M., Nov.-Dec. 02, pp. 83-89.Blaauw, D.,and L. Lavagno, "Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference," Special DAC Section, July-Aug. 02, pp. 72-73.Blanton, R.D.,Nag, P.K., Jan.-Feb. 02, pp. 29-41.Blough, D.,Mooney, V., Nov.-Dec. 02, pp. 44-51.Bogliolo, A.,Dalpasso, M., Sept.-Oct. 02, pp. 92-104.Bordelon, J.,et al., "A Strategy for Mixed-Signal Yield Improvement," May-June 02, pp. 14-23.Breant, F.,Liem, C., Nov.-Dec. 02, pp. 27-35.Brunkhorst, V.,Barnhart, C., Sept.-Oct. 02, pp. 65-73.Buchenrieder, K.J.,Schulz, S., Mar.-Apr. 02, pp. 60-69.CCai, Y.,B. Laquai, and K. Luehman, "Jitter Testing for Gigabit Serial Communication Transceivers," Jan.-Feb. 02, pp. 66-74.Caldwell, A.E.,A.B. Kahng, and I.L. Markov, "Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms," May-June 02, pp. 72-81.Castágne, J.,Rudack, M., Jan.-Feb. 02, pp. 6-17.Cesário, W.,et al., "Multiprocessor SoC Platforms: A Component-Based Design Approach," Nov.-Dec. 02, pp. 52-63.Chang, N.,Shin, D., July-Aug. 02, pp. 7-17.Chen, L.,Krstic, A., July-Aug. 02, pp. 18-27.Cheng, K.-T.,Krstic, A., July-Aug. 02, pp. 18-27.Chen, H.-M.,Huang, I.-J., July-Aug. 02, pp. 28-38.Chen, Z.,et al., " IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions," Mar.-Apr. 02, pp. 24-33.Chiusano, S.,Benso, A., May-June 02, pp. 94-105.Chowdhary, A.,and R. Gupta, "A Methodology for Synthesis of Data Path Circuits," Nov.-Dec. 02, pp. 90-100.Coitinho, R.M.,Galup-Montoro, C., Mar.-Apr. 02, pp. 50-58.Cota, K.,Daasch, W., Sept.-Oct. 02, pp. 74-81.Craig, M.,Bordelon, J., May-June 02, pp. 14-23.DDaasch, R.,Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.Daasch, W.,et al., "Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort," Sept.-Oct. 02, pp. 74-81.Dalpasso, M.,A. Bogliolo, and L. Benini, "Virtual Simulation of Distributed IP-Based Designs," Sept.-Oct. 02, pp. 92-104.De, V.,Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.Dey, S.,Krstic, A., July-Aug. 02, pp. 18-27.Dey, S.,Lahiri, K., July-Aug. 02, pp. 118-130.Diaz-Nava, M.,Cesário, W., Nov.-Dec. 02, pp. 52-63.Dill, D.L.,Shimizu, K., July-Aug. 02, pp. 96-106.Distler, F.,Barnhart, C., Sept.-Oct. 02, pp. 65-73.Dupont, E.,M. Nicolaidis, and P. Rohr, "Embedded Robustness IPs for Transient-Error-Free ICs," May-June 02, pp. 56-70.FFarnsworth, O.,Barnhart, C., Sept.-Oct. 02, pp. 65-73.Favalli, M.,and C. Metra, "Online Testing Approach for Very Deep-Submicron ICs," Mar.-Apr. 02, pp. 16-23.Ferko, A.,Barnhart, C., Sept.-Oct. 02, pp. 65-73.GGalup-Montoro, C.,M.C. Schneider, and R.M. Coitinho, "Resizing Rules for MOS Analog-Design Reuse," Mar.-Apr. 02, pp. 50-58.Gangwal, O.P.,Rutten, M.J., July-Aug. 02, pp. 39-50.Gattiker, A.,Nag, P.K., Jan.-Feb. 02, pp. 29-41.Gauthier, L.,Cesário, W., Nov.-Dec. 02, pp. 52-63.Ghosh, S.,McLaurin, T., May-June 02, pp. 8-13.Girard, P.,"Survey of Low-Power Testing of VLSI Circuits," May-June 02, pp. 82-92.Girard, P.,et al., "High Defect Coverage with Low-Power Test Sequences in a BIST Environment," Sept.-Oct. 02, pp. 44-52.González, J.,Aragonès, X., Sept.-Dec. 02, pp. 27-35.Gupta, R.,"Deep-Submicron Challenges," From the EIC, Mar.-Apr. 02, p. 3.Gupta, R.,Chowdhary, A., Nov.-Dec. 02, pp. 90-100.HHawkins, C.,Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.Hilgenstock, J.,Rudack, M., Jan.-Feb. 02, pp. 6-17.Hsiao, M.S.,Sheng, S., Sept.-Oct. 02, pp. 56-64.Huang, C.-J.,C.-F. Wu, and C.-C. Wang, "Image Processing Techniques for Wafer Defect Cluster Identification," Mar.-Apr. 02, pp. 44-48.Huang, I.-J.,et al., "A Retargetable Embedded In-Circuit Emulation Module for Microprocessors," July-Aug. 02, pp. 28-38.Huertas, G.,et al., "Practical Oscillation-Based Test of Integrated Filters," Nov.-Dec. 02, pp. 64-72.Huertas, G.,et al., "Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell," Nov.-Dec. 02, pp. 73-82.Huertas, J.,Huertas, G., Nov.-Dec. 02, pp. 64-72.Huertas, J.,Huertas, G., Nov.-Dec. 02, pp. 73-82.IIvanov, A.,Tabatabaei, S., May-June 02, pp. 24-36.JJadhav, S.,Liem, C., Nov.-Dec. 02, pp. 27-35.Jaspers, E.G.T.,Rutten, M.J., July-Aug. 02, pp. 39-50.Jerraya, A.,Cesário, W., Nov.-Dec. 02, pp. 52-63.Jin, Y.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Joo, Y.,Shin, D., July-Aug. 02, pp. 7-17.Juan, C.-N.,Huang, I.-J., July-Aug. 02, pp. 28-38.KKahng, A.B.,"The Cost of Design," The Road Ahead, July-Aug. 02, pp. 136,135.Kahng, A.B.,"The Significance of Packaging," The Road Ahead, Nov.-Dec. 02, pp. 104-105.Kahng, A.B.,"Variability," The Road Ahead, May-June 02, pp. 120,116.Kahng, A.B.,Caldwell, A.E., May-June 02, pp. 72-81.Kao, C.-F.,Ing-Jer Huang, July-Aug. 02, pp. 28-38.Keller, B.,Barnhart, C., Sept.-Oct. 02, pp. 65-73.Keshavarzi, A.,Chen, Z., Mar.-Apr. 02, pp. 24-33.Keshavarzi, A.,et al., "Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits," Sept.-Oct. 02, pp. 36-43.Keutzer, K.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Kim, J.,Shin, D., July-Aug. 02, pp. 7-17.Koenemann, B.,Barnhart, C., Sept.-Oct. 02, pp. 65-73.Kondratyev, A.,and K. Lwin, "Design of Asynchronous Circuits Using Synchronous CAD Tools," July-Aug. 02, pp. 107-117.Krstic, A.,et al., "Embedded Software-Based Self-Test for Programmable Core-Based Designs," July-Aug. 02, pp. 18-27.Kulkarni, C.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Kumar Goel, S.,Vermeulen, B., May-June 02, pp. 37-45.LLahiri, K.,S. Dey, and A. Raghunathan, "Communication-Based Power Management," July-Aug. 02, pp. 118-130.Lai, W.-C.,Krstic, A., July-Aug. 02, pp. 18-27.Landrault, C.,Girard, P., Sept.-Oct. 02, pp. 44-52.Laquai, B.,Cai, Y., Jan.-Feb. 02, pp. 66-74.Lavagno, L.,Blaauw, D., July-Aug. 02, pp. 72-73.Leupers, R.,"Compiler Design Issues for Embedded Processors," July-Aug. 02, pp. 51-58.Levia, O.,Liem, C., Nov.-Dec. 02, pp. 27-35.Liem, C.,et al., "Embedded Tools for a Configurable and Customizable DSP Architecture," Nov.-Dec. 02, pp. 27-35.Lombardi, F.,Zhao, J., Jan.-Feb. 02, pp. 54-64.Luehman, K.,Cai, Y., Jan.-Feb. 02, pp. 66-74.Lu, T.-A.,Huang, I.-J., July-Aug. 02, pp. 28-38.Lwin, K.,Kondratyev, A., July-Aug. 02, pp. 107-117.Lyonnard, D.,Cesário, W., Nov.-Dec. 02, pp. 52-63.MMadangarli, V.,Bordelon, J., May-June 02, pp. 14-23.Madge, R.,Daasch, W., Sept.-Oct. 02, pp. 74-81.Magarshack, P.,"Improving SoC Design Quality through a Reproducible Design Flow," Jan.-Feb. 02, pp. 76-83.Malik, S.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Maly, W.,Nag, P.K., Jan.-Feb. 02, pp. 29-41.Markov, I.L.,Caldwell, A.E., May-June 02, pp. 72-81.Martin, G.,"Guest Editor's Introduction: The Reuse of Complex Architectures," Nov.-Dec. 02, pp. 4-5.Marwedel, P.,"Guest Editor's Introduction: Processor-Based Designs," July-Aug. 02, pp. 5-6.Maxwell, P.,Segura, J., Sept.-Oct. 02, pp. 5-7.McLaurin, T.,and S. Ghosh, "ETM10 Incorporates Hardware Segment of IEEE P1500," May-June 02, pp. 8-13.McNames, J.,Daasch, W., Sept.-Oct. 02, pp. 74-81.Metra, C.,Favalli, M., Mar.-Apr. 02, pp. 16-23.Meyer, F.J.,Jun Zhao, Jan.-Feb. 02, pp. 54-64.Mihal, A.,et al., "Developing Architectural Platforms: A Disciplined Approach," Nov.-Dec. 02, pp. 6-16.Moch, S.,Rudack, M., Jan.-Feb. 02, pp. 6-17.Moll, F.,Aragonès, X., Sept.-Oct.. 02, pp. 27-35.Mooney, V.,and D. Blough, "A Hardware-Software Real-Time Operating System Framework for SoCs," Nov.-Dec. 02, pp. 44-51.Moskewicz, M.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Müller, D.,Siegmund, R., July-Aug. 02, pp. 84-95.NNag, P.K.,et al., "Modeling the Economics of Testing: A DFT Perspective," Jan.-Feb. 02, pp. 29-41.Narendra, S.,Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.Nicolaidis, M.,Dupont, E., May-June 02, pp. 56-70.Nicolescu, G.,Cesário, W., Nov.-Dec. 02, pp. 52-63.OO'Farrell, R.,Liem, C., Nov.-Dec. 02, pp. 27-35.Olgaard, C.,Ozev, S., Sept.-Oct. 02, pp. 82-91.Onodera, T.,Barnhart, C., Sept.-Oct. 02, pp. 65-73.Orailoglu, A.,Bayraktaroglu, I., Jan.-Feb. 02, pp. 42-53.Orailoglu, A.,Ozev, S., Sept.-Oct. 02, pp. 82-91.Ozev, S.,C. Olgaard, and A. Orailoglu, "Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers," Sept.-Oct. 02, pp. 82-91.PPateras, S.,"IP for Embedded Diagnosis," May-June 02, pp. 46-55.Paulin, P.,C. Pilkington, and E. Bensoudane, "StepNP: A System-Level Exploration Platform for Network Processors," Nov.-Dec. 02, pp. 17-26.Paulin, P.G.,and M. Santana, "FlexWare: A Retargetable, Embedded-Software Development Environment," July-Aug. 02, pp. 59-69.Paviot, Y.,Cesário, W., Nov.-Dec. 02, pp. 52-63.Peralías, E.,Huertas, G., Nov.-Dec. 02, pp. 64-72.Peralías, E.,Huertas, G., Nov.-Dec. 02, pp. 73-82.Perrott, M.H.,"Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits," July-Aug. 02, pp. 74-83.Pilkington, C.,Paulin, P., Nov.-Dec. 02, pp. 17-26.Pineda de Gyvez, J.,Rodríguez Montañés, P., Sept.-Oct. 02, pp. 18-26.Pol, E.-J.D.,Rutten, M.J., July-Aug. 02, pp. 39-50.Pravossoudovitch, S.,Girard, P., Sept.-Oct. 02, pp. 44-52.Prinetto, P.,Benso, A., May-June 02, pp. 94-105.RRaghunathan, A.,Lahiri, K., July-Aug. 02, pp. 118-130.Redeker, M.,Rudack, M., Jan.-Feb. 02, pp. 6-17.Renovell, M.,F. Azais, and Y. Bertrand, "Improving Defect Detection in Static-Voltage Testing," Nov.-Dec. 02, pp. 83-89.Rodríguez Montañés, R.,P. Volf, and J. Pineda de Gyvez, "Resistance Characterization for Weak Open Defects," Sept.-Oct. 02, pp. 18-26.Rohr, P.,Dupont, E., May-June 02, pp. 56-70.Roy, K.,Chen, Z., Mar.-Apr. 02, pp. 24-33.Roy, K.,Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.Rozenblit, J.W.,Schulz, S., Mar.-Apr. 02, pp. 60-69.Rubio, A.,Aragonès, X., Sept.-Oct. 02, pp. 27-35.Rudack, M.,et al., "A Large-Area Integrated Multiprocessor System for Video Applications," Jan.-Feb. 02, pp. 6-17.Rueda, A.,Huertas, G., Nov.-Dec. 02, pp. 64-72.Rueda, A.,Huertas, G., Nov.-Dec. 02, pp. 73-82.Rutten, M.J.,et al., "A Heterogeneous Multiprocessor Architecture for Flexible Media Processing," July-Aug. 02, pp. 39-50.Ryan, R.,Liem, C., Nov.-Dec. 02, pp. 27-35.SSabade, S, and D.M.H. Walker, " IDDQ Test: Will It Survive the DSM Challenge?" Sept.-Oct. 02, pp. 8-16.Sachdev, M.,Keshavarzi, A., Sept.-Oct. 02, pp. 8-16.Santana, M.,Paulin, P.G., July-Aug. 02, pp. 59-69.Sauer, C.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Schneider, M.C.,Galup-Montoro, C., Mar.-Apr. 02, pp. 50-58.Schulz, S.,K.J. Buchenrieder, and J.W. Rozenblit, "Multilevel Testing for Design Verification of Embedded Systems," Mar.-Apr. 02, pp. 60-69.Scott, D.,Barnhart, C., Sept.-Oct. 02, pp. 65-73.Segura, J.,and P. Maxwell, "Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era," Sept.-Oct. 02, pp. 5-7.Shah, N.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Sheng, S.,and M. Hsiao, "Efficient Sequential Test Generation Based on Logic Simulation," Sept.-Oct. 02, pp. 56-64.Shim, H.,Shin, D., July-Aug. 02, pp. 7-17.Shimizu, K.,and D.L. Dill, "Using Formal Specifications for Functional Validation of Hardware Designs," July-Aug. 02, pp. 96-106.Shin, D.,"Energy-Monitoring Tool for Low-Power Embedded Programs," July-Aug. 02, pp. 7-17.Siegmund, R.,and D. Müller, "Automatic Synthesis of Communication Controller Hardware from Protocol Specifications," July-Aug. 02, pp. 84-95.Silveira, L.M.,and N. Vargas, "Characterizing substrate coupling in deep-submicron designs," Mar.-Apr. 02, pp. 4-15.Stan, M.R.,"CMOS Circuits with Subvolt Supply Voltages," Mar.-Apr. 02, pp. 34-43.Stitt, G.,and F. Vahid, "Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic," Nov.-Dec. 02, pp. 36-43.TTabatabaei, S.,and A. Ivanov, "Embedded Timing Analysis: A SoC Infrastructure," May-June 02, pp. 24-36.Timmer, A.,Rutten, M.J., July-Aug. 02, pp. 39-50.Tranchina, B.,Bordelon, J., May-June 02, pp. 14-23.Tsai, M.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Tschanz, J.,Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.VVahid, F.,Stitt, G., Nov.-Dec. 02, pp. 36-43.van der Wolf, P.,Rutten, M.J., July-Aug. 02, pp. 39-50.van Eijndhoven, J.T.J.,Rutten, M.J., July-Aug. 02, pp. 39-50.Vargas, N.,Silveira, L.M., Mar.-Apr. 02, pp. 4-15.Vázquez, D.,Huertas, G., Nov.-Dec. 02, pp. 64-72.Vázquez, D.,Huertas, G., Nov.-Dec. 02, pp. 73-82.Vermeulen, B.,and S. Kumar Goel, "Design for Debug: Catching Design Errors in Digital Chips," May-June 02, pp. 37-45.Virazel, A.,Girard, P., Sept.-Oct. 02, pp. 44-52.Vissers, K.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Volf, P.,Rodríguez Montañés, Sept.-Oct. 02, pp. 18-26.WWalker, D.M.H.,Sabade, S. Sept.-Oct. 02, pp. 8-16.Wang, C.-C.,Huang, C.-J., Mar.-Apr. 02, pp. 44-48.Weber, S.,Mihal, A., Nov.-Dec. 02, pp. 6-16.Wei, L.,Chen, Z., Mar.-Apr. 02, pp. 24-33.Wei, S.,Nag, P.K., Jan.-Feb. 02, pp. 29-41.Wheater, D.,Aitken, R., Sept.-Oct. 02, pp. 54-55.Wu, C.-F.,Huang, C.-J., Mar.-Apr. 02, pp. 44-48.Wunderlich, H.J.,Girard, P., Sept.-Oct. 02, pp. 44-52.YYoo, S.,Cesário, W., Nov.-Dec. 02, pp. 52-63.Yun, H.-S.,Shin, D., July-Aug. 02, pp. 7-17.ZZhao, J.,F.J. Meyer, and F. Lombardi, "Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems," Jan.-Feb. 02, pp. 54-64.Zorian, Y.,"Guest Editor's Introduction: What Is Infrastructure IP?" May-June 02, pp. 5-7.SUBJECT INDEXAnalog circuitsdeep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.testing mixed-signal cores, practical oscillation-based test in analog macrocell, Huertas, G., et al., Nov.-Dec. 02, pp. 73-82.Analog-digital conversionmixed-signal, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.Application-specific ICsLHC high-energy phys, expts., MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Application-specific ICs,Mixed analog-digital ICsAsynchronous circuitssynchronous, CAD tools, Kondratyev, A., et al., July-Aug. 02, pp. 107-117.Automatic optical inspectionwafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.Automatic testingvery deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.Automatic testing,Automatic test-pattern generation, Automatic test softwareAutomatic test-pattern generationETM10 incorporates hardware segment of IEEE P1500, McLaurin, T., et al., May-June 02, pp. 8-13.Automatic test softwarewafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.Boundary scan testingLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Built-in safe testhigh defect coverage with low-power test sequences in BIST environment, Girard, P., et al., Sept.-Oct. 02, pp. 44-52.Built-in self-testembedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.low-power VLSI circuit, testing, Girard, P., May-June 02, pp. 82-92.scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.CADdesign automation, special DAC section, July-Aug. 02, pp. 72-130.design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.CAD,Electronic design automation, Logic CADCalorimetry,Particle calorimetryCells (electric)battery-driven system-level power management, Lahiri, K., et al., July-Aug. 02, pp. 118-130.Circuit analysis computing,Circuit simulationCircuit CADCAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.Circuit CAD,Hardware description languagesCircuit layout,IC layoutCircuit simulationCMOS circuits, with subvolt supply voltages, Stan, M.R., Mar.-Apr. 02, pp. 34-43.fractional-N frequency, synthesizers, behavioral simulation, Perrott, M.H., July-Aug. 02, pp. 74-83.scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.Circuit testingbus-structured systems, interconnect faults, analysis/diagnosis, Zhao, J., et al., Jan.-Feb. 02, pp. 54-64.Circuit testing,IC testingCircuit theory,Network synthesis, Network topologyCluster toolswafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.CMOS ICsdeep-submicron IC, IDDQ testing, Chen, Z., et al., Mar.-Apr. 02, pp. 24-33.defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.defect-oriented testing in the deep-submicron era, guest editors' introduction, Segura, J., et al., Sept.-Oct. 02, pp. 5-7.leakage and process variation effects in current testing on future CMOS circuits, Keshavarzi, A., et al., Sept.-Oct. 02, pp. 36-43.subvolt supply voltages, Stan, M.R., Mar.-Apr. 02, pp. 34-43.Colliding beam acceleratorsLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Computer applications,CADComputer architecturedisciplined approach to develop architectural platforms, Mihal, A., et al., Nov.-Dec. 02, pp. 6-16.embedded tools for configurable and customizable DSP architecture, Liem, C., et al., Nov.-Dec. 02, pp. 27-35.energy advantages of microprocessor platforms with on-chip configurable logic, Stitt, G., et al., Nov.-Dec. 02, pp. 36-43.hardware-software real-time operating system framework for SoCs, Mooney, V., et al., Nov.-Dec. 02, pp. 44-51.StepNP, system-level exploration platform for network processors, Paulin, P., et al., Nov.-Dec. 02, pp. 17-26.Computer architecture,Parallel architectures, Reconfigurable architecturesComputer debuggingretargetable embedded in-circuit, emulation module for microprocessors, Huang, I.-J., et al., July-Aug. 02, pp. 28-38.Computer interfaces,System busesComputerized instrumentation,High-energy physics instrumentation computingComputer testingon-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.CoprocessorsEclipse, heterogeneous, multiprocessor architecture, for flexible media, Rutten, M.J., et al., July-Aug. 02, pp. 39-50.Cost-benefit analysisIC testing, DFT economics, Nag, P.K., et al., Jan.-Feb. 02, pp. 29-41.test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.Crosstalkdeep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.Cyclic accelerators,Storage rings, SynchrotronsData acquisitionLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Data conversion,Analog-digital conversion, Digital-analog conversionDefect statesdefect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.defect-oriented testing in the deep-submicron era, guest editors' introduction, Segura, J., et al., Sept.-Oct. 02, pp. 5-7.Delaysvery deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.Design costcost of design, Kahng, A.B., The Road Ahead, Nov.-Dec. 02, pp. 136, 135.Design engineeringleakage and process variation effects in current testing on future CMOS circuits, Keshavarzi, A., et al., Sept.-Oct. 02, pp. 36-43.deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.design and test education in Latin America (LATW 2001 Roundtable), May-June 02, pp. 106-113.design automation, special DAC section, July-Aug. 02, pp. 72-130.design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.disciplined approach to develop architectural platforms, Mihal, A., et al., Nov.-Dec. 02, pp. 6-16.embedded systems, special issue, July-Aug. 02, pp. 5-69.embedded systems, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.high defect coverage with low-power test sequences in BIST environment, Girard, P., et al., Sept.-Oct. 02, pp. 44-52.infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.ITC, special ITC section, Sept.-Oct. 02, pp. 54-91.ITC, guest editors' introduction, Aitken, R., et al., Sept.-Oct. 02, pp. 54-55.methodology for synthesis of data path circuits, Chowdhary, A., et al., Nov.-Dec. 02, pp. 90-100.multiprocessor SoC platforms, component-based design approach, Cesário, W., et al., Nov.-Dec. 02, pp. 52-63.test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.variability The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.virtual simulation of distributed IP-based designs, Dalpasso, M., et al., Sept.-Oct. 02, pp. 92-104.Design for testabilitydeep-submicron design and testing, special issue, Mar.-Apr. 02, pp. 3-58.deep-submicron design and testing, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.defect-oriented testing in the deep-submicron era, guest editors' introduction, Segura, J., et al., Sept.-Oct. 02, pp. 5-7.design automation, special DAC section, July-Aug. 02, pp. 72-130.design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.IC testing, DFT economics, Nag, P.K., et al., Jan.-Feb. 02, pp. 29-41.LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.Digital-analog conversionmixed-signal, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.Digital arithmetic,CoprocessorsDigital computers,Parallel machinesDigital filters,Median filtersDigital integrated circuits,Integrated logic circuits, Microprocessor chipsDigital signal processing chipsembedded tools for configurable and customizable DSP architecture, Liem, C., et al., Nov.-Dec. 02, pp. 27-35.Digital simulation,Virtual machinesDigital storage,Random-access storageDigital systems,Multiprocessing systems, Real-time systemsDirect energy conversion,Cells (electric)Distributed processingvirtual simulation of distributed IP-based designs, Dalpasso, M., et al., Sept.-Oct., 02, pp. 92-104.Distributed processing,Multiprocessing systems, Parallel processingEconomics,IC economicsEducationdesign and test education in Latin America (LATW 2001 Roundtable), May-June 02, pp. 106-113.Electrical engineering computing,Automatic test softwareElectrical faults,Fault locationElectric resistance measurementresistance characterization for weak open defects, Rodríguez Montañés, R., et al., Sept.-Oct. 02, pp. 18-26.Electric variables measurement,Voltage measurementElectrochemical devices,Cells (electric)Electron device manufacturing,IC manufacturingElectronic design automationCAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.design automation, special DAC section, July-Aug. 02, pp. 72-130.design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.Verilog and other standards, Ashenden, P.J., Jan.-Feb. 02, pp. 84-85.Electronic design automation,Circuit CADElectronic engineering,Low-power electronicsElectronic engineering computing,Electronic design automation, Logic CAD, Logic simulationElectronic equipment testing,Circuit testing, Telecommunication equipment testingEmbedded systemsEclipse, heterogeneous, multiprocessor architecture for flexible media, Rutten, M.J., et al., July-Aug. 02, pp. 39-50.embedded systems, special issue, July-Aug. 02, pp. 5-69.embedded systems, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.embedded systs., design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.embedded tools for configurable and customizable DSP architecture, Liem, C., et al., Nov.-Dec. 02, pp. 27-35.FlexWare, retargetable embedded software development environment, Paulin, P.G., et al., July-Aug. 02, pp. 59-69.infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.retargetable compiler design for embedded processors, Leupers, R., July-Aug. 02, pp. 51-58.retargetable embedded in-circuit, emulation module for microprocessors, Huang, I.-J., et al., July-Aug. 02, pp. 28-38.SES energy monitoring tool for low-power embedded programs, Shin, D., et al., July-Aug. 02, pp. 7-17.Engineering,Design engineeringEngineering computing,Virtual machinesEstimation theory,Sequential estimationFault currents,Leakage currentsFault diagnosisbus-structured systems, interconnect fault, analysis/diagnosis, Zhao, J., et al., Jan.-Feb. 02, pp. 54-64.scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.Fault diagnosis,Fault locationFault locationvery deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.Field effect analog ICs,MOS analog ICsField programmable gate arraysLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Filterspractical oscillation-based test of integrated filters, Huertas, G., et al., Nov.-Dec., 02, pp. 64-72.Formal specificationcommunication, controller hardware, automatic synthesis, Siegmund, R., et al., July-Aug. 02, pp. 84-95.embedded systems, design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.hardware designs, functional validation using formal specifications, Shimizu, K., et al., July-Aug. 02, pp. 96-106.variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.Formal verificationembedded systems, design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.hardware designs, functional validation using formal specifications, Shimizu, K., et al., July-Aug. 02, pp. 96-106.Frequency synthesizersfractional-N frequency, synthesizers, behavioral simulation, Perrott, M.H., July-Aug. 02, pp. 74-83.Hardware description languagesfractional-N frequency, synthesizers, behavioral simulation, Perrott, M.H., July-Aug. 02, pp. 74-83.Hardware-software codesignhardware-software real-time operating system framework for SoCs, Mooney, V., et al., Nov.-Dec. 02, pp. 44-51.embedded systems, design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.High energy physics instrumentation computingLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.High level synthesis,Hardware-software codesignIEEEconstituting good standard, Standards, Ashenden, P.J., May-June 02, p. 114.variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.IEEE standardsETM10 incorporates hardware segment of IEEE P1500, McLaurin, T., et al., May-June 02, pp. 8-13.IEEE standards process, Ashenden, P.J., Mar.-Apr. 02, pp. 72-73.Verilog and other standards, Ashenden, P.J., Jan.-Feb. 02, pp. 84-85.Image coding,Video codingImage processingdeep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.Industrial propertyCAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.embedded robustness IPs for transient-error-free ICs, Dupont, E., et al., May-June 02, pp. 56-70.intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.Inspection,Automatic optical inspectionIC designCMOS circuits, with subvolt supply voltages, Stan, M.R., Mar.-Apr. 02, pp. 34-43.deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.deep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.IC design,Integrated circuit layoutIC economicsIC testing, DFT economics, Nag, P.K., et al., Jan.-Feb. 02, pp. 29-41.IC layoutMOS analog-design reuse, resizing rules and MOSFET model, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.IC manufacturingwafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.IC manufacturing,IC economicsIC modelingMOS analog-design reuse, resizing rules and MOSFET model, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.ICsdeep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.ITC, special ITC section, Sept.-Oct. 02, pp. 54-91.ITC, guest editors' introduction, Aitken, R., et al., Sept.-Oct. 02, pp. 54-55.variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.IC testingdeep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.deep-submicron IC, IDDQ testing, Chen, Z., et al., Mar.-Apr. 02, pp. 24-33.DFT economics, Nag, P.K., et al., Jan.-Feb. 02, pp. 29-41.embedded robustness IPs for transient-error-free ICs, Dupont, E., et al., May-June 02, pp. 56-70.embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.low-power VLSI circuit testing, Girard, P., May-June 02, pp. 82-92.very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.Integrated logic circuitstesting mixed-signal cores, practical oscillation-based test in analog macrocell, Huertas, G., et al., Nov.-Dec. 02, pp. 73-82.Interconnectionsbus-structured systems, interconnect fault, analysis/diagnosis, Zhao, J., et al., Jan.-Feb. 02, pp. 54-64.Interference (signal),CrosstalkJittergigabit serial communication, transceivers, jitter testing, Yi Cai, et al., Jan.-Feb. 02, pp. 66-74.SoC infrastructure, embedded timing analysis, Tabatabaei, S., et al., May-June 02, pp. 24-36.Large-scale integration,VLSILeakage currentsdeep-submicron IC, IDDQ testing, Chen, Z., et al., Mar.-Apr. 02, pp. 24-33.Localized states,Defect statesLogicefficient sequential test generation based on logic simulation, Sheng, S., et al., Sept.-Oct. 02, pp. 56-64.Logic,Logic design, Logic simulation, Logic testingLogic CADasynchronous circuits, synchronous CAD tools, Kondratyev, A., et al., July-Aug. 02, pp. 107-117.Logic circuits,Asynchronous circuits, Integrated logic circuitsLogic designdesign for debug, catching design errors in digital chips, Vermeulen, B., et al., May-June 02, pp. 37-45.mixed-signal, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.SoC infrastructure, embedded timing analysis, Tabatabaei, S., et al., May-June 02, pp. 24-36.Logic design,Logic partitioningLogic partitioningscan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.Logic simulationITC, special ITC section, Sept.-Oct. 02, pp. 54-91.ITC, guest editors' introduction, Aitken, R., et al., Sept.-Oct. 02, pp. 54-55.scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.Logic testingdesign for debug, catching design errors in digital chips, Vermeulen, B., et al., May-June 02, pp. 37-45.embedded robustness IPs for transient-error-free ICs, Dupont, E., et al., May-June 02, pp. 56-70.embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.ETM10 incorporates hardware segment of IEEE P1500, McLaurin, T., et al., May-June 02, pp. 8-13.intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.mixed-signal, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.SoC infrastructure, embedded timing analysis, Tabatabaei, S., et al., May-June 02, pp. 24-36.very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.Low-power electronicsbattery-driven, system-level power management, Lahiri, K., et al., July-Aug. 02, pp. 118-130.deep-submicron IC, IDDQ testing, Chen, Z., et al., Mar.-Apr. 02, pp. 24-33.low-power VLSI circuit testing, Girard, P., May-June 02, pp. 82-92.subvolt supply voltages, Stan, M.R., Mar.-Apr. 02, pp. 34-43.Management,Cost-benefit analysisManufacturinginfrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.Mathematical analysis,Time-domain analysisMeasurementvariability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.Median filterswafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.Meetingsdesign and test education in Latin America, LATW 2001 Roundtable, May-June 02, pp. 106-113.test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.Microprocessor chipsembedded systems, special issue, July-Aug. 02, pp. 5-69.embedded systems, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.multiprocessor SoC platforms, component-based design approach, Cesário, W., et al., Nov.-Dec. 02, pp. 52-63.retargetable embedded in-circuit, emulation module for microprocessors, Huang, I.-J., et al., July-Aug. 02, pp. 28-38.Microprocessor chips,Coprocessors, Digital signal processing chipsMISFET,MOSFETMixed analog-digital ICsdeep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.mixed-sig, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.Modelingtest economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.Modeling,IC modeling, Semiconductor device modelsModules,Multichip modulesMonolithic ICs,Application-specific ICsMOS analog ICsresizing rules for MOS analog-design reuse, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.MOSFETresizing rules and MOSFET model for MOS analog-design reuse, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.MOS ICs,CMOS ICs, MOS analog ICsMultichip modulesLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.significance of packaging, Kahng, A.B., The Road Ahead, Nov.-Dec. 02, pp. 104-105.Multiprocessing systemsEclipse, heterogeneous multiprocessor architecture for flexible media, Rutten, M.J., et al., July-Aug. 02, pp. 39-50.large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.on-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.Multiprocessor interconnection networksapplication-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.Network routingon-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.Networks (circuits)infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.methodology for synthesis of data path circuits, Chowdhary, A., et al., Nov.-Dec. 02, pp. 90-100.Networks (circuits),Analog circuits, Coupled circuits, Filters, Integrated circuits, Oscillators, Phase-locked loopsNetwork synthesisSoC, reproducible design flow, Magarshack, P., Jan.-Feb. 02, pp. 76-83.Network synthesis,Circuit CAD, IC designNetwork topologyapplication-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.Noise generatorsnoise generation and coupling mechanisms in deep-submicron ICs, Aragonès, X., et al., Sept.-Oct. 02, pp. 27-35.Nuclear electronicsLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Operating systems (computers)hardware-software real-time operating system framework for SoCs, Mooney, V., et al., Nov.-Dec. 02, pp. 44-51.Optimizing compilersretargetable compiler design for embedded processors, Leupers, R., July-Aug. 02, pp. 51-58.Oscillationspractical oscillation-based test of integrated filters, Huertas, G., et al., Nov.-Dec., 02, pp. 64-72.Oscillatorstesting mixed-signal cores, practical oscillation-based test in analog macrocell, Huertas, G., et al., Nov.-Dec. 02, pp. 73-82.Packaging,Multichip modulesParallel architectureson-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.Parallel machineson-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.Parallel processingapplication-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.Parallel processing,Parallel architectures, Parallel machinesParticle accelerators,Colliding beam acceleratorsParticle calorimetryLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Performance evaluationimproving defect detection in static-voltage testing, Renovell, M., et al., Nov.-Dec. 02, pp. 83-89.variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.Performance evaluation,Software performance evaluationPhase locked loopsfractional-N frequency, synthesizers, behavioral simulation, Perrott, M.H., July-Aug. 02, pp. 74-83.Physics computing,High-energy physics instrumentation computingPlatform-based designPlatform-based design of SoCs, special issue, Nov.-Dec. 02, pp. 4-63.Platform-based design of SoCs, guest editor's introduction, Nov.-Dec. 02, pp. 4-5.Power consumptionbattery-driven, system-level power management, Lahiri, K., et al., July-Aug. 02, pp. 118-130.Program compilersembedded systems, special issue, July-Aug. 02, pp. 5-69.embedded processors, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.embedded tools for configurable and customizable DSP architecture, Liem, C., et al., Nov.-Dec. 02, pp. 27-35.Program compilers,Optimizing compilersProgram debuggingintellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.Program diagnosticsinfrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.Programmable logic arrays,Field-programmable gate arraysProgramming,Program testing, Software toolsProgram processorsStepNP, system-level exploration platform for network processors, Paulin, P., et al., Nov.-Dec. 02, pp. 17-26.Program processors,Program compilersProgram testingembedded systems, design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.Protocolscommunication, controller hardware, automatic synthesis, Siegmund, R., et al., July-Aug. 02, pp. 84-95.Radiation detection,Particle calorimetryRadio equipment,TransceiversRandom-access storageon-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.Readout electronicsLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Real-time systemshardware-software real-time operating system framework for SoCs, Mooney, V., et al., Nov.-Dec. 02, pp. 44-51.intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.Real-time systems,Embedded systemsReconfigurable architecturesEclipse, heterogeneous multiprocessor architecture for flexible media, Rutten, M.J., et al., July-Aug. 02, pp. 39-50.Redundancylarge-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.Reliabilityinfrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.Satellite computers,CoprocessorsSemiconductor counters,Silicon radiation detectorsSemiconductor device modelsMOS analog-design reuse, resizing rules and MOSFET model, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.Sequential estimationefficient sequential test generation based on logic simulation, Sheng, S., et al., Sept.-Oct. 02, pp. 56-64.Signal generators,Frequency synthesizers, Noise generatorsSignal processing,Digital signal processing chips, Image processingSilicon radiation detectorsLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Simulationefficient sequential test generation based on logic simulation, Sheng, S., et al., Sept.-Oct. 02, pp. 56-64.virtual simulation of distributed IP-based designs, Dalpasso, M., et al., Sept.-Oct. 02, pp. 92-104.Simulation,Circuit simulation, Logic simulationSmoothing methods,Median filtersSoftware engineering,Formal specification, Formal verification, Software performance evaluation, Software reusability, Software toolsSoftware performance evaluationSES energy monitoring tool for low-power embedded programs, Shin, D., et al., July-Aug. 02, pp. 7-17.Software reusabilityCAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.Software toolsFlexWare, retargetable embedded software development environment, Paulin, P.G., et al., July-Aug. 02, pp. 59-69.SES energy monitoring tool for low-power embedded programs, Shin, D., et al., July-Aug. 02, pp. 7-17.Special issues and sectionsapplication-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.design automation, special DAC section, July-Aug. 02, pp. 72-130.embedded systems, special issue, July-Aug. 02, pp. 5-69.infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.ITC, special ITC section, Sept.-Oct. 02, pp. 54-91.test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.Specification languages,Hardware description languagesStandardsconstituting good standard, Standards, Ashenden, P.J., May-June 02, p. 114.variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.Standards,IEEE standardsStorage ringsLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.Substratesdeep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.Switching networks,Multiprocessor interconnection networksSynchrotronsLHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.System busesinterconnect fault, analysis/diagnosis, Zhao, J., et al., Jan.-Feb. 02, pp. 54-64.System monitoringimproving defect detection in static-voltage testing, Renovell, M., et al., Nov.-Dec. 02, pp. 83-89.System monitoring,Program diagnosticsSystems analysisinfrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.Systems software,Operating systems (computers), Program processors, System monitoringTelecommunication equipment testinggigabit serial communication, transceivers, jitter testing, Cai, Y., et al., Jan.-Feb. 02, pp. 66-74.Testingdeep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.defect-oriented testing in the deep-submicron era, guest editors' introduction, Segura, J., et al., Sept.-Oct. 02, pp. 5-7.design and test education in Latin America (LATW 2001 Roundtable), May-June 02, pp. 106-113.design automation, special DAC section, July-Aug. 02, pp. 72-130.design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.efficient sequential test generation based on logic simulation, Sheng, S., et al., Sept.-Oct. 02, pp. 56-64.embedded systems, special issue, July-Aug. 02, pp. 5-69.embedded systems, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.extending OPMISR beyond 10x scan test efficiency, Barnhart, C., et al., Sept.-Oct. 02, pp. 65-73.high defect coverage with low-power test sequences in BIST environment, Girard, P., et al., Sept.-Oct. 02, pp. 44-52.IDDQ test, surviving the DSM challenge, Sabade, S, et al., Sept.-Oct. 02, pp. 8-16.infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.leakage and process variation effects in current testing on future CMOS circuits, Keshavarzi, A., et al., Sept.-Oct., 02, pp. 36-43.multilevel testability analysis and solutions for integrated Bluetooth transceivers, Ozev, S., et al., Sept.-Oct. 02, pp. 82-91.neighborhood selection for IDDQ outlier screening at wafer sort, Daasch, W, et al., Sept.-Oct. 02, pp. 74-81.practical oscillation-based test of integrated filters, Huertas, G., et al., Nov.-Dec., 02, pp. 64-72.testing mixed-signal cores, practical oscillation-based test in analog macrocell, Huertas, G., et al., Nov.-Dec. 02, pp. 73-82.Testing,Automatic testing, Boundary scan testing, Built-in self test, Computer testing, Logic testing, Program testingTime-domain analysisSoC infrastructure, embedded timing analysis, Tabatabaei, S., et al., May-June 02, pp. 24-36.Timingvery deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.Topology,Network topologyTransceiversgigabit serial communication transceivers, jitter testing, Yi Cai, et al., Jan.-Feb. 02, pp. 66-74.multilevel testability analysis and solutions for integrated Bluetooth transceivers, Ozev, S., et al., Sept.-Oct. 02, pp. 82-91.Video codingapplication-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.Video signal processing,Video codingVirtual machineshardware designs, functional validation using formal specifications, Shimizu, K., et al., July-Aug. 02, pp. 96-106.VLSICAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.low-power VLSI circuit, testing, Girard, P., May-June 02, pp. 82-92.very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.VLSI,Wafer-scale integrationVoltage measurementimproving defect detection in static-voltage testing, Renovell, M., et al., Nov.-Dec. 02, pp. 83-89.Wafer-scale integrationdeep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.
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