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Issue No. 06 - November/December (2002 vol. 19)
ISSN: 0740-7475
pp: 90-100
<p>This methodology extracts the regularity of data path blocks from their HDL descriptions and preserves it throughout the synthesis process. By automating various design steps, the methodology significantly improves design productivity and achieves designs comparable in terms of delay and size to manually designed circuits. </p>
Rajesh Gupta, Amit Chowdhary, "A Methodology for Synthesis of Data Path Circuitse", IEEE Design & Test of Computers, vol. 19, no. , pp. 90-100, November/December 2002, doi:10.1109/MDT.2002.1047748
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