The Community for Technology Leaders
Green Image
ABSTRACT
<p>A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digitalcircuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.</p>
INDEX TERMS
CITATION

P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel and H. Wunderlich, "High Defect Coverage with Low-Power Test Sequences in a BIST Environment," in IEEE Design & Test of Computers, vol. 19, no. , pp. 44-52, 2002.
doi:10.1109/MDT.2002.1033791
91 ms
(Ver 3.3 (11022016))