Issue No. 05 - September/October (2002 vol. 19)
<p>A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digitalcircuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.</p>
P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel and H. Wunderlich, "High Defect Coverage with Low-Power Test Sequences in a BIST Environment," in IEEE Design & Test of Computers, vol. 19, no. , pp. 44-52, 2002.