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Issue No. 05 - September/October (2002 vol. 19)
ISSN: 0740-7475
pp: 27-35
On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models. This new demand for test technology practices precipitated the investigation of dl/dt and dV/dt noise generation and propagation mechanisms.
semiconductor device noise, integrated circuit testing,multiple digital gates, deep-submicron technologies, IC technology, test techniques, physical failures, parasitic coupling, noise generation,Noise generators, Pins, Electronics packaging, Circuit testing, Inductance, Power supplies, Parasitic capacitance, Coupling circuits, Bonding, Variable structure systems
"Noise generation and coupling mechanisms in deep-submicron ICs", IEEE Design & Test of Computers, vol. 19, no. , pp. 27-35, September/October 2002, doi:10.1109/MDT.2002.1033789
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