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Issue No.03 - May/June (2002 vol.19)
pp: 24-36
ABSTRACT
<p>This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure a variety of timing-related SoC characteristics, including jitter. The ETIA requires little design and area overhead and performs accurately under process and environment variation and noise.</p>
CITATION
Sassan Tabatabaei, André Ivanov, "Embedded Timing Analysis: A SoC Infrastructure", IEEE Design & Test of Computers, vol.19, no. 3, pp. 24-36, May/June 2002, doi:10.1109/MDT.2002.1003786
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