Issue No. 03 - May/June (2002 vol. 19)
P. Girard , Lab. of Informatics Robotics & Microelectron., Montpellier, France
The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.
built-in self test, integrated circuit testing, VLSI, low-power electronics
P. Girard, "Survey of low-power testing of VLSI circuits," in IEEE Design & Test of Computers, vol. 19, no. 3, pp. 82-92, .