Issue No. 01 - January/February (2002 vol. 19)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.980050
<p>By dividing testing into three phases-router, RAM block, and processors-this strategy ensures an efficient tradeoff of test quality and cost.</p>
C. Aktouf, "A Complete Strategy for Testing an On-Chip Multiprocessor Architecture," in IEEE Design & Test of Computers, vol. 19, no. , pp. 18-28, 2002.