Issue No. 06 - November/December (2001 vol. 18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.970420
<p>Addressing fundamental challenges to designing high-performance ICs in nanometer-scale technologies, the authors advocate a flexible approach to limiting both dynamic and static power. They recommend global-signaling strategies to curb communication power requirements and thermal management techniques to ease the burden on packaging.</p>
H. Kaul and D. Sylvester, "Power-Driven Challenges in Nanometer Design," in IEEE Design & Test of Computers, vol. 18, no. , pp. 12-22, 2001.