• Wojciech Maly describes the design and test cost problem and its solution: geometric regularity and reuse.
• Kurt Keutzer proposes programmability and programmable platforms as another workaround for crises in cost and turnaround time.
• Vinod Agarwal presents the promise of embedded test.
• Joseph Borel discusses the roadmap process and whether it is even identifying the right showstoppers.
• Raul Camposano describes the response of the EDA industry to technology drivers.
William H. Joyner Jr. is a research staff member at IBM on assignment as director of computer-aided design and test at Semiconductor Research Corp. He also cochairs the US Design Technology Working Group for the 2001 ITRS. His research interests include logic synthesis, physical design, and verification. Joyner has a BS in engineering science from the University of Virginia and a PhD in applied mathematics from Harvard University. He is a Fellow of the IEEE.
Andrew B. Kahng is a professor of computer science and engineering, and electrical and computer engineering, at the University of California, San Diego. He chairs the US Design Technology Working Group and the Design International Technology Working Group for the 2001 ITRS renewal. His research interests include VLSI physical design and performance analysis, measurement and improvement of design technology and processes, combinatorial and graph algorithms, and stochastic global optimization. Kahng has an AB in applied mathematics (physics) from Harvard College, and an MS and PhD in computer science from the University of California, San Diego.