Issue No. 05 - September/October (2001 vol. 18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.953276
<p>This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints.</p>
P. Prinetto, S. Chiusano, M. L. Bondoni, A. Benso and G. D. Natale, "Online and Offline BIST in IP-Core Design," in IEEE Design & Test of Computers, vol. 18, no. , pp. 92-99, 2001.