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ABSTRACT
<p>Assembling a system on a chip using IP blocks is an error-prone, labor-intensive, and time-consuming process. Emerging high-level tools can help by automating many of the design tasks.</p>
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CITATION
Foster White, Reinaldo A. Bergamaschi, Michael Muhlada, Subhrajit Bhattacharya, William R. Lee, Ronoldo Wagner, Colleen Fellenz, Jean-Marc Daveau, "Automating the Design of SOCs Using Cores", IEEE Design & Test of Computers, vol. 18, no. , pp. 32-45, September/October 2001, doi:10.1109/54.953270
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