Issue No. 05 - September/October (2001 vol. 18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.953270
<p>Assembling a system on a chip using IP blocks is an error-prone, labor-intensive, and time-consuming process. Emerging high-level tools can help by automating many of the design tasks.</p>
F. White et al., "Automating the Design of SOCs Using Cores," in IEEE Design & Test of Computers, vol. 18, no. , pp. 32-45, 2001.