Issue No. 04 - July/August (2001 vol. 18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.936249
Several proposed hardware architectures for fuzzy processors satisfy real-time requirements, but very few are suitable for automatic synthesis. This bit-scalable architecture allows automatic synthesis of fuzzy processors of various bit-wide
O. Saotome, K. H. Kienitz and R. d'Amore, "A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors," in IEEE Design & Test of Computers, vol. 18, no. , pp. 56-64, 2001.