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ABSTRACT
CAD tool designers have given priority to providing features that will let circuit and logic designers use this custom-memory formal verification and analysis tool without a steep learning curve.
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CITATION

M. S. Abadir, J. A. Abraham, N. Krishnamurthy and A. K. Martin, "Design and Development Paradigm for Industrial Formal Verification CAD Tools," in IEEE Design & Test of Computers, vol. 18, no. , pp. 26-35, 2001.
doi:10.1109/54.936246
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