Issue No. 04 - July/August (2001 vol. 18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.936246
CAD tool designers have given priority to providing features that will let circuit and logic designers use this custom-memory formal verification and analysis tool without a steep learning curve.
M. S. Abadir, J. A. Abraham, N. Krishnamurthy and A. K. Martin, "Design and Development Paradigm for Industrial Formal Verification CAD Tools," in IEEE Design & Test of Computers, vol. 18, no. , pp. 26-35, 2001.