Issue No. 04 - July/August (2001 vol. 18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.936244
The author explores applying formal Boolean equivalence verification to the RTL design flow, and introduces an effective equivalence-checking usage model that ensures optimal benefits in an RTL static sign-off methodology.
H. Foster, "Applied Boolean Equivalence Verification and RTL Static Sign-Off," in IEEE Design & Test of Computers, vol. 18, no. , pp. 6-15, 2001.