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Issue No.03 - May/June (2001 vol.18)
pp: 83-97
A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.
Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane, "System-on-Chip Testability Using LSSD Scan Structures", IEEE Design & Test of Computers, vol.18, no. 3, pp. 83-97, May/June 2001, doi:10.1109/54.922805
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