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ABSTRACT
A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.
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CITATION

K. Zarrineh, S. J. Upadhyaya and V. Chickermane, "System-on-Chip Testability Using LSSD Scan Structures," in IEEE Design & Test of Computers, vol. 18, no. , pp. 83-97, 2001.
doi:10.1109/54.922805
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