, Advantest America R & D Inc.
Pages: pp. 3-4
As applications continually grow in complexity and size, data storage technology becomes increasingly important. Many new applications and systems must contend with severe bottlenecks because of the data access speed, size, and power consumption associated with this storage. This problem is particularly prevalent in embedded systems, especially in battery-powered communication and computer systems. Moreover, designing new systems is more difficult because of increasingly complex memory modules, such as synchronous DRAMs and enhanced-data-output and double-data-rate memories, as well as the advent of more flexible, partly software-controllable caches. In more customized, deeply embedded applications, distributed on-chip memory organizations involving larger on-chip memory units than the traditional design style are solving the access and power-consumption-bottleneck problems.
System-on-a-chip denotes the integration of random logic, processor cores, SRAMs, ROMs, and analog components on the same piece of silicon. But until recently, one major component had been missing: high-density memories such as DRAM and flash memory. Today's technologies allow the integration of significant amounts of DRAM and flash memory for applications such as data buffering and the storage of video frames, voice, and application-specific programs and data. Up to 128 Mbits of DRAM and 500,000 gates of logic are feasible in 0.25-μm technologies. This capacity tremendously enlarges the system design space, so system architects are no longer restricted to off-chip commodity memories.
This special issue discusses the opportunities and challenges in using large embedded memories in application design. The issue also reviews the memory mapping/compilation, architecture, technology, and test issues involved in large embedded memories.
The first article, "Embedded DRAM Development: Technology, Physical Design, and Application Issues," by Doris Keitel-Schulz and Norbert Wehn, provides background on embedded-DRAM process, circuit, and market issues. The main emphasis is on opportunities and challenges from the application designer's viewpoint.
The next article, "Design and Test of Large Embedded Memories: An Overview," by Rochit Rajsuman, further discusses the technology behind, and motivation for, using large embedded memories. After reviewing a few specific design and simulation aspects of large embedded memories generated by automated tools, the article discusses fault models, test algorithms, and design-for-test methods. It also discusses memory redundancy, repair, and test implementation issues.
Memory redundancy and repair are essential for yield improvement. Hence, an article on yield learning follows the overview of redundancy analysis and repair. "Using Electrical Bitmap Results from Embedded Memory to Enhance Yield," by Julie Segal and her colleagues, describes the use of bitmaps for realistic fault prediction and yield learning.
"Random-Access Data Storage Components in Customized Architectures," by Lode Nachtergaele, Francky Catthoor, and Chidamber Kulkarni, investigates building blocks and overall storage organizations in customized memory architectures. The main emphasis is on modern application-specific multimedia and telecommunications-oriented processors.
To use these increasingly complex memory organizations, the design methodology and application designer's tool support must change. The last two articles address the issues in system design technology and compilation for embedded data-dominated multimedia applications that use embedded memories: "Data Memory Organization and Optimizations in Application-Specific Systems," by Preeti Ranjan Panda and his colleagues, surveys the emerging techniques that allow a retargetable memory platform mapping. "Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors," by Francky Catthoor and his colleagues, describes a methodology for platform-independent source-to-source transformations. Such transformations allow cost-efficient mapping.
The articles in this special issue have strong tutorial content. We intend them as an introduction to the exciting new domain of embedded memories for system and application design engineers, technology developers, and test engineers. This special issue does not provide a detailed state-of-the-art discussion (for experts in the subdomains); such detailed discussion with a consistent flow would require multiple issues of any magazine. However, our contributors have given appropriate points and referenced articles with complementary views. We hope you find this material useful as background, or perhaps even as a starting point, for your journey in this very promising new technology.
We thank the editorial board and staff of IEEE Design & Test of Computers. Special thanks are due to Yervant Zorian, Ahmed Jerraya, and Cheri Yoast. We also gratefully acknowledge contributions by many others, including all the unnamed reviewers: Without their work, this issue would not be possible.