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An Electronic System usually contains heterogenous components that may be active at different times. In other words, component activity is event-driven. A simple, yet effective approach to reduce the power dissipated by the system consists of disabling (or reducing the performance of) the components when they are inactive (or partially unexploited). Dynamic power management (DPM) is a design methodology that allows power-down (or slow-down) of system components to provide requested services and performance levels with minimum power consumption.
A component of an event-driven computing system can be modeled through a finite state machine that, in the simplest case, has two states: active and idle. When the component is idle, it can be shut down by lowering its power supply or by turning off its clock; this can drastically reduce power dissipation.
Time-out Policies
The simplest DPM policies are time-out-based. A component is put in its power-down mode only T time units after its finite state machine model has entered the idle state. It is assumed there is a high chance for the component to continue to be idle after having been in the idle state for at least T time units.
Time-out policies can be inefficient for three reasons. First, the assumption that if the component is idle for more than T time units it will continue to be so may not be true in many cases. Second, whenever the component enters the idle state, it stays powered for at least T time units, wasting a considerable amount of power during that period. Third, speed and power degradations caused by shutdowns performed at inappropriate times are not taken into account. In fact, it should be kept in mind that the transition from power-down to fully functional mode has an overhead. It takes some time to bring the system up to speed, and it may also take more power than the average, steady-state power.
More Complex DPM Policies
To overcome time-out-based policy limitations, more complex strategies have been developed. Predictive, adaptive, and stochastic strategies are a few examples of effective policies. These strategies are based on complex mathematical models and all try to exploit the past history of active and idle intervals to predict the next idle period's length, deciding whether it is convenient to power down a system component.
Beside component idleness, component underutilization can also be successfully exploited to limit power consumption. For example, if a processing unit operating at full speed requires less time to complete a given task than the actual performance constraint, execution time (and thus power) can be reduced by making the processor run slower. This can be achieved by either reducing the clock frequency, or lowering the supply voltage, or both, provided that hardware and software enable this type of operation. In all cases, substantial power savings are obtained with no performance penalty. Policies for dynamic clock and voltage control are of increasing popularity in electronic products that feature DPM capabilities.
Other DPM Implementation Issues
In addition to policy development, several other issues must be considered when implementing DPM in practice. These include

    • the need for models of power-managed systems,

    • the choice of an implementation style for a power manager that must guarantee accuracy in measuring interarrival times and service times for the system components,

    • flexibility in monitoring multiple components,

    • low perturbation, and

    • marginal impact on component usage.

Also key is the style choice for monitoring component activity; options here are offline, in which the system dumps event traces for later analysis; and online, in which event traces are analyzed while the system is running, and statistics related to component usage are constantly updated.
DPM is, by far, the most successful approach to power optimization that has found wide usage in real-life cases. Transmeta's Crusoe processor is a representative application example of DPM in practice. For this reason, many researchers have recently made a substantial effort to develop innovative DPM solutions. This special issue will review the most advanced and promising contributions to various aspects of DPM in electronic systems.
Industrial Perspective
We start by giving an industrial perspective of the applicability of DPM in real environments. In particular, two major portable electronics market players, Hewlett-Packard and Compaq, present their own experiences of what has been achieved so far and what open problems and challenges require further investigation.
Facets of DPM
A total of six contributed papers are included in this special issue. The opening article provides a classification of existing DPM policies, discusses each approach's pros and cons, and quantitatively compares their power savings, performance penalties, and resource requirements. A practical example of implementing DPM on a laptop computer running Microsoft Windows 2000 closes the article.
The second contribution addresses the problem of intratask voltage scheduling. In particular, it presents an algorithm for automatically assigning voltages to different basic blocks of programs with hard real-time constraints. Code transformations are applied at compile time, although the inserted voltage-scaling instructions can require dynamic (that is runtime) information in deciding the proper voltage value at each point in time. The proposed algorithm's validation has been carried out on a program implementing MPEG-4 video decoding.
Intertask supply-voltage scheduling is the third article's subject. The authors survey static and dynamic scheduling techniques for assigning voltages to tasks of a real-time application with tight performance constraints. They then compare these techniques experimentally to highlight various algorithms' advantages and drawbacks.
The fourth article discusses the application of DPM techniques within asynchronous processors. These techniques range from simple circuit design solutions to architectural design features; some are peculiar to asynchronous environments, while others are equally applicable in the synchronous domain. The authors use the Amulet family of processors to illustrate the proposed techniques.
The fifth article introduces the concept of battery-driven DPM, which seeks to enhance battery life by automatically adapting the discharge rate and current profiles required by a digital application to the battery's state of charge. The authors compare the performance of several battery-oriented DPM policies for a portable, digital audio recorder.
Finally, the last article presents an application example of DPM in the context of microelectromechanical systems. More specifically, they introduce modeling and power optimization techniques based on DPM for massively distributed wireless microsensor networks and provide experimental benchmark data.
Up to now, only the simplest forms of DPM have been used. However, as shown by the research work collected in this special issue, the spectrum of opportunities fitting the DPM paradigm is huge. Integration of prototypes and academic proposals into a variety of real-life products should be expected to happen soon.

Enrico Macii is an associate professor of computer engineering at Politecnico di Torino. His research interests include several computer-aided design of integrated circuits and systems aspects, with particular emphasis on synthesis, optimization, and formal verification. Macii has a DrEng in electrical engineering and a PhD in computer engineering from Politecnico di Torino, Italy, and a DrSc in computer science from Universita diTorino.
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