, Politecnico di Torino
Pages: pp. 6-9
An Electronic System usually contains heterogenous components that may be active at different times. In other words, component activity is event-driven. A simple, yet effective approach to reduce the power dissipated by the system consists of disabling (or reducing the performance of) the components when they are inactive (or partially unexploited). Dynamic power management (DPM) is a design methodology that allows power-down (or slow-down) of system components to provide requested services and performance levels with minimum power consumption.
A component of an event-driven computing system can be modeled through a finite state machine that, in the simplest case, has two states: active and idle. When the component is idle, it can be shut down by lowering its power supply or by turning off its clock; this can drastically reduce power dissipation.
The simplest DPM policies are time-out-based. A component is put in its power-down mode only T time units after its finite state machine model has entered the idle state. It is assumed there is a high chance for the component to continue to be idle after having been in the idle state for at least T time units.
Time-out policies can be inefficient for three reasons. First, the assumption that if the component is idle for more than T time units it will continue to be so may not be true in many cases. Second, whenever the component enters the idle state, it stays powered for at least T time units, wasting a considerable amount of power during that period. Third, speed and power degradations caused by shutdowns performed at inappropriate times are not taken into account. In fact, it should be kept in mind that the transition from power-down to fully functional mode has an overhead. It takes some time to bring the system up to speed, and it may also take more power than the average, steady-state power.
To overcome time-out-based policy limitations, more complex strategies have been developed. Predictive, adaptive, and stochastic strategies are a few examples of effective policies. These strategies are based on complex mathematical models and all try to exploit the past history of active and idle intervals to predict the next idle period's length, deciding whether it is convenient to power down a system component.
Beside component idleness, component underutilization can also be successfully exploited to limit power consumption. For example, if a processing unit operating at full speed requires less time to complete a given task than the actual performance constraint, execution time (and thus power) can be reduced by making the processor run slower. This can be achieved by either reducing the clock frequency, or lowering the supply voltage, or both, provided that hardware and software enable this type of operation. In all cases, substantial power savings are obtained with no performance penalty. Policies for dynamic clock and voltage control are of increasing popularity in electronic products that feature DPM capabilities.
In addition to policy development, several other issues must be considered when implementing DPM in practice. These include
Also key is the style choice for monitoring component activity; options here are offline, in which the system dumps event traces for later analysis; and online, in which event traces are analyzed while the system is running, and statistics related to component usage are constantly updated.
DPM is, by far, the most successful approach to power optimization that has found wide usage in real-life cases. Transmeta's Crusoe processor is a representative application example of DPM in practice. For this reason, many researchers have recently made a substantial effort to develop innovative DPM solutions. This special issue will review the most advanced and promising contributions to various aspects of DPM in electronic systems.
We start by giving an industrial perspective of the applicability of DPM in real environments. In particular, two major portable electronics market players, Hewlett-Packard and Compaq, present their own experiences of what has been achieved so far and what open problems and challenges require further investigation.
A total of six contributed papers are included in this special issue. The opening article provides a classification of existing DPM policies, discusses each approach's pros and cons, and quantitatively compares their power savings, performance penalties, and resource requirements. A practical example of implementing DPM on a laptop computer running Microsoft Windows 2000 closes the article.
The second contribution addresses the problem of intratask voltage scheduling. In particular, it presents an algorithm for automatically assigning voltages to different basic blocks of programs with hard real-time constraints. Code transformations are applied at compile time, although the inserted voltage-scaling instructions can require dynamic (that is runtime) information in deciding the proper voltage value at each point in time. The proposed algorithm's validation has been carried out on a program implementing MPEG-4 video decoding.
Intertask supply-voltage scheduling is the third article's subject. The authors survey static and dynamic scheduling techniques for assigning voltages to tasks of a real-time application with tight performance constraints. They then compare these techniques experimentally to highlight various algorithms' advantages and drawbacks.
The fourth article discusses the application of DPM techniques within asynchronous processors. These techniques range from simple circuit design solutions to architectural design features; some are peculiar to asynchronous environments, while others are equally applicable in the synchronous domain. The authors use the Amulet family of processors to illustrate the proposed techniques.
The fifth article introduces the concept of battery-driven DPM, which seeks to enhance battery life by automatically adapting the discharge rate and current profiles required by a digital application to the battery's state of charge. The authors compare the performance of several battery-oriented DPM policies for a portable, digital audio recorder.
Finally, the last article presents an application example of DPM in the context of microelectromechanical systems. More specifically, they introduce modeling and power optimization techniques based on DPM for massively distributed wireless microsensor networks and provide experimental benchmark data.
Up to now, only the simplest forms of DPM have been used. However, as shown by the research work collected in this special issue, the spectrum of opportunities fitting the DPM paradigm is huge. Integration of prototypes and academic proposals into a variety of real-life products should be expected to happen soon.
Hewlett-Packard products span many different types of computing devices, ranging from sub-personal digital assistants, such as calculators, through PDAs, laptops, desktops, servers and their networks, home appliances, and home networks. Energy consumption has become one primary concern because of the need for longer battery life in portable devices and environmental concerns related to desktops and servers.
Thanks to its effectiveness and flexibility, dynamic power management is one technique HP portable products rely upon to reduce system power. Among the available DPM policies, the most common and simple, yet less efficient, are the time-out-based ones. Predictive policies increase achievable savings by forcing a transition to a low-power state as soon as a component becomes idle only if the predictor estimates that the idle period will last long enough. Both time-out and predictive policies are heuristic, and thus do not guarantee optimal results.
In contrast, policies derived from stochastic models can guarantee optimal results. They use distributions to describe the times between arrivals of service requests, the length of time for a device to service a request, and the time the device takes to transition between its power states. The system model for stochastic optimization can be described either with memoryless distributions (exponential or geometric) or with general distributions, the latter being the most effective. 1 Power savings range from two- to fivefold when implemented on the SmartBadge portable device, a laptop hard-disk, and a wireless local area network (WLAN) card. 2
DPM implementation in real systems has several issues that still need to be resolved. A critical problem is the lack of operating system support for power management. ACPI (Advanced Configuration and Power Interface) has enabled a standard interface for power management in systems running Windows 2000. 3 For devices such as sub-PDAs, which deploy small-footprint embedded OSs, there is little or no OS support for DPM. An additional problem is that not all hardware components in a device support controllable power states. For example, a WLAN card interface typically has none. A consequence is that the PDA has an eight-hour battery life without the WLAN, but this figure drops to little more than two hours with WLAN use. Even with systems that have full OS and hardware support for power management, it would help to have smart applications that inform the power manager of their energy needs. In this way, the power manager, together with the OS, can schedule processes to maximize idle times and thus enable larger energy savings.
The last area where power management has large potential savings is at the level of networked home appliances and servers. In such systems, the gateway should actively participate in appliance power management. The electricity cost for just one PC-class processor with storage elements can be as much as $140 US per year when operating 24 hours per day. Since homes may have many such appliances, the yearly operating cost could become significant. Allowing remote power activation control using a networked mechanism such as a gateway or advanced network interface can save significant energy while maintaining 24-hour connected functionality.ReferencesT.SimunicL.BeniniandG.De Micheli"Dynamic Power Management for Portable Systems,"Proc. 6th Int'l Conf. Mobile Computing and Networking,ACM,Boston, Mass.,2000,pp. 11-19.G.Q.MaguireM.SmithandH.W. PeterBeadle"SmartBadges: A Wearable Computer and Communication System,"6th Int'l Workshop on Hardware/Software Codesign,ACM,Boston, Mass.,1998.Intel/Microsoft/Toshiba"Advanced Configuration and Power Interface Specification,"http://www.teleport.com/acpi/.
Modern portable systems have many parameters that affect power consumption. For example, speaker volume, liquid crystal display (LCD) backlight intensity, microprocessor power savings modes, clock speed, supply voltage, number of active memory banks, and wireless-link output power can all be varied. To minimize energy consumption, a clear understanding of how varying system parameters will affect the energy required for a given task is needed. We believe that the best approach is to provide computers with the ability to continuously measure their own power consumption and to optimize energy use in real time.
There is a simple relationship between some parameters and overall power consumption. For example, power consumption monotonically increases with backlight intensity, without regard to other system parameters, therefore the backlight is easy to manage. Other parameters, however, can couple in unintuitive ways. The interaction of clock speeds and low-power processor modes is of particular interest.
The Itsy, designed at Compaq's Palo Alto research laboratories, is a high-performance, low-power, pocket computer, capable of running traditional desktop applications. 1 We characterized Itsy's average power consumption for various processor modes (run, idle, and sleep) while running several applications. Decreasing the clock frequency from 206 to 59 MHz while the system is mostly idle cuts power by 30 percent. When playing an audio file, however, the same frequency reduction only saved 10 percent, because the power dissipated by the speaker is independent of clock frequency.
The behavior running the Digital Equipment Corp. DECtalk text-to-speech application is subtler. At 74 MHz, the processor runs continuously, and all cycles are dedicated to speech synthesis. At 206 MHz, there are periods where the processor is in idle mode. However, the power consumption in both cases is nearly identical. The clock speed, static power dissipation in complementary metal-oxide semiconductor (CMOS) circuits, and the energy cost of memory accesses, all play a role in this interesting result. Varying the processor core voltage adds yet another dimension: For the DECtalk example, we can save an additional 10 percent at 74 MHz. Our results further suggest that even in single application usage scenarios, there are cases where running at the highest clock speed followed by sleep mode periods will give the lowest average power consumption.
The situation becomes even more complex when a unit can offload computation to a remote server using a radio link. There is a trade-off between the power cost of radio operation and the power savings of remote computation that varies with application, transport medium, transmission distance, and even available bandwidth. Quality-of-service considerations and external server performance further complicate the optimization process.
Fine-grained power measurements let system software construct a static model that can be used to optimize energy use. For a fixed application set, such as an embedded system, these measurements could be taken using external lab instruments. However, for a changing application set, built-in power monitoring facilities, such as those provided in the recent Itsy versions, are necessary. They also allow an even more aggressive scenario: to have the system continuously probe and model the effect of parameter variations and perform local-energy optimization in real time. Also, it's easier to build a system that could vary quality-of service or fidelity to match a fixed battery endurance requirement. All are avenues of potentially fruitful research.ReferencesJ.F.Bartlettet al.,"The Itsy Pocket Computer,"research report 2000/6, Western Research Laboratories, Compaq Computer Corp.,Palo Alto, Calif.,2000.