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This paper presents a hierarchical modeling technique which, when combined with a test pattern generation algorithm, forms a hierarchical automatic test pattern generation procedure for analog circuits and systems. This hierarchical procedure is demonstrated to be efficient in terms of both memory and computational speed, especially in processing large circuits. Several examples illustrate the hierarchical modeling technique. The test generation algorithm has been validated in several case studies, one of which is described in details. A prototype software tool is available for university and industry use, with possible enhancements to increase the tool applicability in specific design and test environments.

G. Devarayanadurg, S. Huynh, J. Zhang, S. Kim and M. Soma, "Hierarchical ATPG for Analog Circuits and Systems," in IEEE Design & Test of Computers, vol. 18, no. , pp. 72-81, 2001.
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