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Logic fault diagnosis or fault isolation is the process of analyzing the failing logic portions of an integrated circuit to isolate the cause of failure. Fault diagnosis plays an important role in multiple applications at different stages of design and manufacturing. A logic diagnosis tool with applicability to a spectrum of logic DFT, ATPG and test strategies including full/almost full-scan circuits with combinational APTG, partial-scan and non-scan circuits with sequential APTG and to functional patterns in general is presented. Novel features incorporated into the tool include static and dynamic structural processing for partial-scan circuits, windowed fault simulation, and diagnostic models for open defects and cover algorithms for multiple fault diagnosis. Experimental results include simulation results on processor functional blocks and silicon results on chipsets and processors from artificially induced defects and production fallout.
Diagnosis and Debugging, Logic Fault Diagnosis, Interconnect Open and Bridge Defects, Diagnostic Fault Modeling and Simulation, Dynamic Diagnosis.

S. B. Drummonds and S. Venkataraman, "Poirot: Applications of a Logic Fault Diagnosis Tool," in IEEE Design & Test of Computers, vol. 18, no. , pp. 19-30, 2001.
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