, Northeastern University
, University of Bologna
Pages: pp. 8-9
This special issue consists of five articles that have been selected to cover a wide spectrum of techniques that are encountered in the defect-driven diagnosis as commonly employed in the manufacturing of today's computer systems.
Recent years have seen the rapid emergence of very deep submicron technology for the design of digital chips; the reduction in geometry and the ever-increasing density of these devices have been widely advocated by the Semiconductor Industry Association (SIA) as two of the most pressing endeavors facing the technology road map in the years ahead. The process encountered in the manufacturing of such complicated chips requires a substantial departure from traditional practice. The process of detecting and locating defects and faults (commonly known as diagnosis) plays a pivotal role in attaining acceptable yields and reducing production costs. While in the past, fault detection and location were considered two distinct steps for achieving diagnosis, in very deep submicron technology their roles are indivisible and very demanding.
Today, diagnosis faces many challenges. A full characterization of the underlying phenomena is required to provide the technological basis on which radical changes can be implemented for efficient and practical solutions. Coordinated efforts have been undertaken to provide a better understanding of all steps involved in a diagnostic technique; related aspects must be fully addressed in a cohesive manner to provide the designer with a complete suite of tools.
This task is more difficult when sometimes-conflicting requirements cause multiple test sets to be applied to the different stages of design and manufacturing. This is evident at both tester and unit-under-test ends. Isolation of the possible causes of failure requires a very precise calibration process in the tester to take into account technology-related variation effects. This results in considerable difficulty in improving existing methodologies for selecting the correct faulty element out of possibly many candidates. Due to strict requirements such as precise identification and location, and the presence of a large volume of tester data, this is a daunting task. Automated tools to enable design or fabrication process modifications require a substantially different framework as currently provided by emulating accurate emulation of real defects. Salient features (such as at-speed testing and high coverage) must be retained. Also, the time/space efficiency of this process must be taken into account from the onset. It is the convergence of all of these issues that make diagnosis in very deep submicron technology a relevant, but extremely difficult, objective.
Our first article describes how atomic force microscopy employs a raster scanning method to image the area of a surface with a variety of probe tips for different diagnostic purposes. An atomic force microscopy technique, which utilizes a beam-bounce method of feedback control is proposed as a viable alternative to FIB (focused ion beam) for failure analysis of submicron structures, its ability of cutting at nanometer scales is investigated. Experimental results are provided to substantiate the viability of atomic force microscopy technique due to its enhanced resolution and preciseness compared with traditional FIB methodologies.
S. Venkataraman and S.B. Drummonds present a tool for automated logic diagnosis. Poirot handles both the logic DFT and ATPG scenarios. Structural and logical analysis and diagnostic fault models (inclusive of opens and shorts) are extensively analyzed by comparing the observed behavior from the tester with a faulty candidate's predicted behavior. In this tool, a window of vectors is set up for simulating each failing pattern during diagnosis; multiple faults are handled through a partitioning technique for high-volume manufacturing.
The next article, by J. Dworak et al. has a quantitative evaluation of the correlation between the single stuck-at fault model and bridging defects is pursued. The role of excitation and observation in defect detection is dealt in depth; the analysis uses OBDD simulation to illustrate the correlation between the overlap of the testing spaces of faults and defects as fault coverage increases. It is shown that using coverage as a metric, the prediction of defective part level becomes less reliable at high values.
The next two articles deal with I DDQ techniques of reliability screening for diagnostic purposes. I DDQ has received considerable attention as it has been widely reported that there is a significant increase in subthreshold leakage currents, thus making it difficult to set an absolute and reliable pass/fail threshold at the deep submicron level.
K. Muhammad et al. address a technique for attaining diagnosis at a normal speed of operation. The proposed procedure periodically tests the circuit under test on a module-by-module basis; whenever a module is in the idle state, diagnostic routines are executed. This article shows that for detection the fast Fourier transform method represents a more powerful option. Location of a fault is pursued in levelized circuits by measuring the delay at which the current waveform of a good circuit deviates from the response of a faulty circuit.
J. Plusquellic and C. Patel extend transient signal analysis (now called quiescent signal analysis, or QSA) using I DDQ measured at multiple supply pins to localize defects. QSA consists of two phases. Each supply pin sources a unique fraction of the total I DDQ drawn by the defect, thus determining the equivalent resistance between each supply pin and the defect size. Various calibration procedures for measuring process- and technology-related leakage currents are proposed based on a linear regression analysis. It is shown that for fault location, this technique is best used in combination with a fault dictionary.
We sincerely hope that this special issue will be a reference publication for future research. We extend our sincere thanks to all the authors and reviewers. We also thank Yervant Zorian, editor-in-chief of IEEE Design and Test of Computers, for allowing us to create this special issue.