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We address the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructions. This is because no instruction sequence can produce a test sequence which can sensitize the path and capture the fault effect into the destination output/flip-flop at-speed. These paths are called functionally untestable paths. We discuss the impact of delay defects on the functionally untestable paths on the overall circuit performance. Identification of such paths helps determine the achievable path delay fault coverage and reduce the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX ) indicate that a significant percentage of structurally testable paths are functionally untestable.
Wei-Cheng Lai, Kwang-Ting (Tim) Cheng, Angela Krstic, "Functionally Testable Path Delay Faults on a Microprocessor", IEEE Design & Test of Computers, vol. 17, no. , pp. 6-14, October-December 2000, doi:10.1109/54.895002
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