Issue No. 03 - July-September (2000 vol. 17)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.867899
<p>The example chip operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains. It also couples a large digital design to a mixed-signal part in physical design.</p>
D. J. Webb, P. Buchmann, A. Herkersdorf and R. Clauberg, "Design Methodology for a Large Communication Chip," in IEEE Design & Test of Computers, vol. 17, no. , pp. 86-94, 2000.