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Issue No.03 - July-September (2000 vol.17)
pp: 86-94
<p>The example chip operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains. It also couples a large digital design to a mixed-signal part in physical design.</p>
Rolf Clauberg, Peter Buchmann, Andreas Herkersdorf, David J. Webb, "Design Methodology for a Large Communication Chip", IEEE Design & Test of Computers, vol.17, no. 3, pp. 86-94, July-September 2000, doi:10.1109/54.867899
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