Issue No. 03 - July-September (2000 vol. 17)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.867892
<p>This article presents a method for inserting test logic at the behavioral level of a VHDL design description. The method is easy to use, and in most cases it requires lower area overhead than classical scan insertion methods.</p>
H. Fleury, C. Aktouf and C. Robach, "Inserting Scan at the Behavioral Level," in IEEE Design & Test of Computers, vol. 17, no. , pp. 34-42, 2000.