Issue No. 02 - April-June (2000 vol. 17)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.844338
<p>This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features.</p>
D. Bhavsar, "Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability," in IEEE Design & Test of Computers, vol. 17, no. , pp. 94-99, 2000.