Issue No. 01 - January-March (1999 vol. 16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.748807
Some people involved in the design and manufacturing of integrated circuits might argue that testability features should not be added to complex or high volume products. These arguments are based on economic analyses which are believed to show that the costs incurred when incorporating design for testability are not recouped in the manufacturing process. However, there are a number of cost avoidance and benefit terms that are often neglected in such calculations. In this artic;e, methods are suggested to estimate values for several of those additional terms. We give as an example the results of the application of the model to the TI TMS320C80, also known as the MVP.
DFT economics, cost estimatation, testabilility, design and test
K. M. Butler, "Estimating the Economic Benefits of DFT," in IEEE Design & Test of Computers, vol. 16, no. , pp. 71-79, 1999.