Issue No. 04 - October-December (1998 vol. 15)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.735924
The authors present a framework for tailoring fault tolerant approaches for both permanent and transient faults to the specific needs of an application. In particular, they address methodologies for encoding fault isolation properties in calculation duplication to allow permanent fault identification, an efficient approach to post-identification reconfiguration using graceful degradation instead of spares, and an error recovery technique which actually recovers from previously detected errors in parallel with future calculations, thus achieving zero-error latency. In conjunction, these techniques provide an efficient alternative to traditional triplication and rollback schemes, and allow significant tailoring of area/resiliency trade-offs for individual designs.
A. Orailoglu and S. N. Hamilton, "Efficient Self-Recovering ASIC Design," in IEEE Design & Test of Computers, vol. 15, no. , pp. 25-35, 1998.