The Community for Technology Leaders
Green Image
Issue No. 04 - October-December (1998 vol. 15)
ISSN: 0740-7475
pp: 12-16
Very large scale integration has become an important implementation technology for many application domains including automotive, communication, medical, and satellite electronics.
Because of the limited on-chip real estate in previous VLSI generations, online testing technology had been restricted to very few application domains, and even there, to a very limited extent. The reduction in VLSI feature sizes and increase in modern VLSI integrated circuit sizes has resulted in an abundance of on-chip interconnect and data path resources, making online VLSI testing affordable.
Furthermore, with transient and intermittent faults becoming a dominant failure mode in modern VLSI, widespread deployment of online VLSI test technology has become crucial. Key benefits of online VLSI testing include fault tolerance at source, low-latency fault detection and correction, and fault effect localization.
We can implement online testing using hardware redundancy (hardware duplication, triplication, and spares), time redundancy (recomputing with shifted operands), information redundancy (error-detecting and error-correcting codes), or parametric testing methods (built-in current sensors). Nicolaidis and Zorian 1 provide a comprehensive survey of online VLSI testing techniques.
The articles selected for this special issue focus on important areas of online testing. Hussain Al-Assad, Brian Murray, and John P. Hayes discuss the development of a systematic framework based on error coverage, error latency, hardware redundancy, and time redundancy. This framework helps designers evaluate the suitability of existing online testing techniques for embedded system applications.
Two articles address the incorporation of online testing constraints during the high-level synthesis phase of a top-down VLSI design methodology. Samuel Hamilton and Alex Orailo $\breve{\bf g}$lu describe techniques for fault detection and isolation via algorithm duplication and on-chip reconfiguration via graceful degradation in data-path-dominated VLSI designs.
Sybille Hellebrand and Hans Wunderlich show us how to make the control units of such data path VLSI designs online testable by partitioning the controller states into groups. They also show how we can constrain the transitions such that they can emanate from states within a group and terminate on states in a different group.
Long clock signal lines in synchronous digital VLSI systems are highly susceptible to transient and intermittent faults. Moreover, the correctness of clock signals distributed across a VLSI circuit is essential for the correct operation of a system. Based on these observations, Cecilia Metra, Michele Favalli, and Bruno Riccò present their design of a self-checking self-checker. It checks whether the clock signals emanating from a single clock source are all simultaneously high (all-1s code) or all simultaneously low (all-0s code).
In contrast to the previously discussed techniques that use hardware, time, or information redundancy for online testing, Jien-Chung Lo makes a strong case for the use of built-in current sensors for both online and production-time monitoring of quiescent (I DDQ) and/or transient (I DD) current in deep-submicron designs.
Automotive electronics is an important application domain in which online testing techniques have been used. Critical automotive functions such as antilock braking, throttle control, and air-bag control have been implemented using microcontrollers. While straightforward duplication with checking yields low error detection latency and negligible performance penalty, it entails more than 100% area/cost overhead. To reduce the costs associated with duplication in checking, researchers at Robert Bosch GmbH have used low-cost online testing techniques such as parity coding and checking, periodic application of BIST, and I DDQ testing of peripherals in their AE11 microcontroller. Eberhard Böhl, Thomas Lindenkreuz, and Matthias Meerwein describe some of the online testing features of AE11.
Finally, Cristiana Bolchini, Fabio Salice, and Donatella Sciuto propose an approach for fault analysis and simulation of complete or partially concurrent error-detecting designs so as to characterize the faults to which a design is susceptible.
We trust you will find this special online VLSI testing issue helpful and interesting as we make the move to a new testing paradigm and techniques that will support our industry for the year 2000 and beyond.
We gratefully acknowledge the help of Editor-in-Chief Yervant Zorian, the authors, the reviewers, and the IEEE Design & Test staff, especially Jason True Seaborn, in putting together this special issue. NSF grant MIP9702676 partially supported Ramesh Karri's work.


Ramesh Karri is an associate professor of electrical engineering at the Polytechnic University, Brooklyn, New York, where he leads the online VLSI testing and reconfigurable computing projects. His main research interests include on- and offline built-in self test, embedded core testing, VLSI synthesis targeting deep-submicron reliability and low power, design of reconfigurable architectures, real-time embedded systems design, and hardware-software codesign. Karri received an MS in computer engineering and a PhD in computer science from the University of California at San Diego. He is a recipient of the NSF Career Award.

Michael Nicolaidis is a research director at the French National Research Center (CNRS) and leader of the Reliable Integrated Systems Group in the TIMA Laboratory. His main research interests include VLSI system testing, online testing, self-checking and fail-safe systems, DFT, BIST, I DDQ testing, mixed-signal testing, and radiation hardened/tolerant systems. Nicolaidis received a degree in electrical engineering from the Polytechnic School of the University of Thessaloniki (Greece) and an engineer Doctorate Thesis from the INPG, Grenoble, France. He is presently vice chair of the IEEE Computer Society Test Technology Technical Committee (TTTC).
169 ms
(Ver 3.3 (11022016))