Issue No.03 - July-September (1998 vol.15)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.706041
Module generators provided by library vendors supply chip designers with optimized Booth multipliers which are widely used, as embedded cores, in both general purpose datapath structures and specialized Digital Signal Processors. Testing of such multipliers deeply embedded in complex ICs requires the utilization of an effective BIST scheme that can be easily synthesized along with the multiplier by the module generator. The BIST scheme for Booth multipliers, introduced in this paper, completely complies with this requirement. The algorithmic BIST patterns that this scheme generates guarantee a fault coverage higher than 99%. The required Test Pattern Generator consists of a simple fixed-size either binary counter or maximum length LFSR, independent of the size of the multiplier. Accumulator-based compaction is adopted since multipliers and adders co-exist in datapath structures. A new accumulator-based compaction scheme is introduced to provide higher compaction quality than existing approaches. The novel BIST scheme is generic, (i.e. independent of specific gate-level implementations of the multiplier cells and not requiring DFT in the multiplier) and thus it can be adopted by any module generator.
Booth multipliers, Built-In Self Test, design for testability, data paths
Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian, "Effective Built-In Self-Test for Booth Multipliers", IEEE Design & Test of Computers, vol.15, no. 3, pp. 105-111, July-September 1998, doi:10.1109/54.706041