Issue No. 03 - July-September (1998 vol. 15)
ISSN: 0740-7475
pp: 64-69
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.706035
ABSTRACT
This article describes the testability features and test pattern development methodologies for the AMD-K6 Microprocessor. The embedded Design for Testability (DFT) structures and test strategy provide high quality manufacturing tests.
INDEX TERMS
AMD-K6, design for testability, test strategies, manufacturing costs
CITATION
R. Scott Fetherston, Siyad C. Ma, Imtiaz P. Shaik, "Testability Features of the AMD-K6 Microprocessor", IEEE Design & Test of Computers, vol. 15, no. , pp. 64-69, July-September 1998, doi:10.1109/54.706035
