Issue No. 03 - July-September (1998 vol. 15)
Each year, for the past 29 years, industry and academic professionals have gathered at the International Test Conference to push forward the state of the art of test. ITC 97 was the biggest conference yet, and the Microprocessor Test sessions offered some of the broadest and most detailed papers ever presented.
In some ways, microprocessor test is a reflection or a superset of today's industrial test issues. Microprocessors challenge us in many ways.
- They are very high speed—which demands accurate equipment and accurate models for test generation.
- They are very highly integrated. Today, designers integrate millions of transistors in complex systems that may be the most complicated designs ever attempted.
- They have complex memory and data architectures—which preclude the simple use of a single approach for test. Embedded-memory complexity rivals stand-alone devices, and the complex logic pushes the test generation process for test tool development.
- They use the most advanced processes—which allows the integration of millions of transistors, yet they are the first to experience the complex defect mechanisms in deep-submicron technology.
- They are high volume and cost sensitive—which forces the design and test staffs to create efficient, production-worthy test processes.
This special section of IEEE Design and Test features articles based on several of the papers presented at the ITC 97 Microprocessor Test sessions. The authors discuss dramatically different methods to achieve high logic and memory test coverage, and each solves one or more microprocessor test problems. We can use the ideas as a basis for testing other devices. Each of the products described is in production with proven quality and manufacturing volume. They demonstrate the practical application of different test techniques.
For instance, each article covers the challenge of testing large embedded caches—which is the major consumer of transistors in all the microprocessors referenced. The methods to achieve the test goals vary widely, but each one acknowledges the need for good memory test. Of special interest is the HP PA8500 article, which focuses on embedded memory test and the algorithms used.
The Alpha, K6, ColdFire, and Pentium Pro authors discuss methods for speed testing, both for binning and delay defects. Pay close attention to the widely different methods of speed test: at-speed functional patterns, at-speed scan, and scan-based delay faults.
Authors also reference I DDQ as a key technology.
Every article covers DFT features for logic, caches, or both. While the methods used differ greatly, all of them achieve the desired final results. S390 is an example of a very rigorous approach to DFT.
Finally, the PowerPC 750 article addresses test program generation and grading.
The authors of these articles have graciously detailed their works with the idea that we will all benefit from their experiences. I thank them all for the high-quality technical material presented here.
Wayne Needham is a principal engineer of test at Intel Corporation in Chandler, Arizona. During his 26 years there, he has held positions in engineering and engineering management, including product, design, and test. He has contributed in some way to the test of the company's major microprocessor, from the 4004 to the Pentium Pro. He has also worked for Hewlett Packard, Signetics, and Memorex.Needham holds a BSEE and MSEE from San Jose State University. He is a senior member of the IEEE, chairs the 1999 International Test Conference Program Committee, and has represented Intel at SIA, SRC, and Sematech.