Issue No. 04 - October-December (1997 vol. 14)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.632883
One of the primary draw-backs of the core-based design paradigm is the limited knowledge of the internal structure and organization of the cores which is provided to the users. This problem is particularly critical from the point of view of testing, since it forces the designers to rely on the test patterns provided by the core vendors. As a solution that avoids the use of scan-based techniques, we present a test methodology which provides the following capabilities: Test generation for a system containing cores, and testability estimation and improvement of the system components. The methodology can be applied to designs consisting of an arbitrary interconnection of modules, some of which may be cores. Our approach relies on a fault model which allows the identification of an accurate correspondence between functional and stuck-at sources of failure. In addition, a functional DfT technique reduces the design to a feedback-free interconnection eventually improving the testability of some modules. This provides an abstraction of the interconnection structure of the system, thus enabling its simplification to a chain of three basic entities: The module under test, a controlling network, and an observing network. The whole methodology exploits the expressiveness of Binary Decision Diagrams for the storage and the manipulation of the system description. Some promising results, conducted on a reasonably complex core-based design, demonstrate the applicability of the proposed approach.
Core-Based Design, Fault Modeling, Test Sequence Generation, Testability Estimation, Implicit Enumeration, Binary Decision Diagrams
F. Ferrandi, D. Sciuto, E. Macii, F. Fummi and M. Poncino, "Testing Core-Based Systems: A Symbolic Methodology," in IEEE Design & Test of Computers, vol. 14, no. , pp. 69-77, 1997.