Issue No. 04 - October-December (1997 vol. 14)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.632881
Core-based designs pose a significant test challenge. A simple and fast solution is to place a full isolation ring (i.e., boundary scan) around each core, however, the area and performance overhead for this may not be acceptable in many applications. A systematic method is presented for designing a partial isolation ring that provides the same fault coverage as a full isolation ring, but avoids adding MUXes on critical timing paths and reduces area overhead. Efficient ATPG techniques are used to analyze the user-defined logic surrounding the core and identify a maximal set of core inputs and outputs that do not need to be included in the partial isolation ring. In the case where one core is driving another core, the procedure identifies a maximal set of isolation ring elements that can be removed from the interface between the cores. Several different partial isolation ring selection strategies that vary in computational complexity are described. Experimental results are shown comparing the different strategies.
Core-based design, testing designs, ATPG, systems on a chip
Nur A. Touba, Bahram Pouya, "Using Partial Isolation Rings to Test Core-Based Designs", IEEE Design & Test of Computers, vol. 14, no. , pp. 52-59, October-December 1997, doi:10.1109/54.632881