Issue No. 02 - April-June (1997 vol. 14)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.587740
<p>Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.</p>
R. A. Bergamaschi and S. Raje, "Observable Time Windows: Verifying High-Level Synthesis Results," in IEEE Design & Test of Computers, vol. 14, no. , pp. 40-50, 1997.