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An ever increasing demand for affordable on-chip fault-tolerance, the inherent unreliability attendant upon very large scale integration (VLSI), and the overwhelming complexity of fault-tolerance have elevated the automatic design of fault-tolerant VLSI systems into a research problem of immediate practical relevance. In this paper, we will outline (i) a flexible methodology for compiling an algorithmic description into an equivalent fault-tolerant VLSI IC subject to an application specific policy for fault-tolerance and (ii) a framework that embodies this methodology. The framework subsumes algorithms for synthesizing self-recovering, fault-secure, and reliable VLSI ICs from high-level algorithmic descriptions.
Fault-Tolerance, High Level Synthesis, CAD

K. Hogstedt, A. Orailoglu and R. Karri, "Computer-Aided Design of Fault-Tolerant VLSI Systems," in IEEE Design & Test of Computers, vol. 13, no. , pp. 88-96, 1996.
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