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A CAD environment for low-power design is presented. The environment supports a high-level approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. This methodology is consistent with current state-of-the-art techniques for low-power design. The framework consists of a set of analysis and optimization tools that span the design hierarchy. These tools are integrated in a way that allows the designer to employ a systematic approach to low-power design through a top-down exploration and refinement of solutions in the area-time-power (ATP) design space. The efficacy of the CAD environment and tools is illustrated by a case study which leads to a low-power implementation of a digital bandpass filter. The proposed approach is shown to lead to more than an order of magnitude savings in power. This result is achieved by a thorough search of the area-time-power design space, which would not have been possible without the assistance of high-level design tools.

R. Mehra, P. Landman and J. M. Rabaey, "An Integrated CAD Environment for Low-Power Design," in IEEE Design & Test of Computers, vol. 13, no. , pp. 72-82, 1996.
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