Issue No.02 - Summer (1996 vol.13)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.500202
A CAD environment for low-power design is presented. The environment supports a high-level approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. This methodology is consistent with current state-of-the-art techniques for low-power design. The framework consists of a set of analysis and optimization tools that span the design hierarchy. These tools are integrated in a way that allows the designer to employ a systematic approach to low-power design through a top-down exploration and refinement of solutions in the area-time-power (ATP) design space. The efficacy of the CAD environment and tools is illustrated by a case study which leads to a low-power implementation of a digital bandpass filter. The proposed approach is shown to lead to more than an order of magnitude savings in power. This result is achieved by a thorough search of the area-time-power design space, which would not have been possible without the assistance of high-level design tools.
Paul Landman, Renu Mehra, Jan M. Rabaey, "An Integrated CAD Environment for Low-Power Design", IEEE Design & Test of Computers, vol.13, no. 2, pp. 72-82, Summer 1996, doi:10.1109/54.500202