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An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate, component functional defect rate and test coverage. A new Yield model which accounts for the clustering of solder defects is introduced, and a first-order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given.
test costs, board faults, dft, board test coverage, yield
Tom W. Chen, Mick M.v. Tegethoff, "Sensitivity Analysis of Critical Parameters in Board Test", IEEE Design & Test of Computers, vol. 13, no. , pp. 58-63, Spring 1996, doi:10.1109/54.485783
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