Issue No. 01 - Spring (1996 vol. 13)
THOUGH THE PROBLEMS of designing and testing complex electronic systems may not be of a different nature in Eastern Europe, solutions developed there often go untold in IEEE publications. This special issue gives readers an opportunity to explore the current status and developing trends of design and test in several Eastern European countries. Current collaborative research efforts, international conferences, and publications such as IEEE D&T are making great strides toward the creation of a single extended design and test community.
The five articles included in this issue cover timely topics such as test synthesis, formal verification, scheduling for high-level synthesis, circuit modeling, and on-line testing. Interestingly, the topics and problems our Eastern European authors address are not different from those usually discussed in D&T. However, these articles place a comparatively greater emphasis on theoretical generalization.
The response to the call for articles for this special issue was unusually rich. Hence, article selection, in general, was a difficult task. We used a a rigorous review procedure involving more than 100 reviewers, one third of them from Eastern Europe. Our intent was to obtain evaluations not only from our pool of expert reviewers, who represent the D&T readership, but also from peers of the Eastern European authors, who may have certain background knowledge about the submitted work. We recommended some of the manuscripts, because of their nature and technical content, for various IEEE transactions or for the Journal of Electronic Testing: Theory and Applications (JETTA).
As the submitted manuscripts represent a good sampling of design and test topics and solutions under scrutiny in Eastern European institutions, we briefly characterize those we were not able to include in this issue.
Synthesis and hardware description
V. Baykov from St. Petersburg State University of Electrical Engineering (Russia) presents hardware algorithms and architectures overlapping serial input with parallel processing. This study in hardware-software codesign aims at using extra hardware to achieve minimum latency and maximum throughput.
A. Zakrevski from the Institute of Engineering Cybernetics in Minsk (Belarus) proposes a parallel control algorithm, its verification, and hardware implementation. This is a theoretical analysis of properties of control algorithm descriptions and their implementations in different contexts.
V. Onofrei, A. Valachi, and S. Radu from Ia i Technical University (Romania) study a matrix method for an efficient tool that performs synthesis of complex synchronous sequential machines. This study covers the idea of decomposing a digital system into control and data parts and then deriving the structure of combinational logic controlling the D flip-flop inputs.
Timing analysis and simulation
V. Dvorak and J. Schwarz from the Technical University in Brno (Czech Republic) present an approach for cross-talk analysis in a multiconductor interconnect system. They propose a theoretical solution to the analysis of multiconductor transmission lines.
Ya.A. Skobtsov from the Institute of Applied Mathematics and Mechanics of the Ukrainian Academy of Sciences in Donetsk (Ukraine) studies multivalued modeling for simulation and test generation. This work maps multivalued alphabets into two- or four-valued ones with the aim of verifying digital systems for timing and hazard analysis, fault simulation, and test pattern generation.
D.C. Dimitrov from the Technical University of Sofia and M.P. Bankova from the High Naval School in Varna (Bulgaria) propose computer simulation of periodical impulse signals with finite spectrum. This manuscript addresses the problems of signal processing. The authors' solution uses extrapolation and interpolation of the spectrum of signals instead of design for testability.
M. Hristov and M.E. Goranova from the Technical University of Sofia (Bulgaria) propose an electronic device modeling technique, and compare measured values with those obtained through SPICE simulation.
B. Benyo and A. Pataricza from the Technical University of Budapest (Hungary) and R. Vemuri from the University of Cincinnati (US) compare algorithmic and random functional-test generation. The authors demonstrate results of test generation on benchmark examples, and they use some structural properties of the generated tests as comparison criteria.
G. Jasineviciene, B. Burgis, R. Kacinskaite, A. Kulikauskas, and M. Surniene from Kaunas University of Technology (Lithuania) describe a high-level hierarchical test generation approach for digital circuits. I.G. Tabakow from the Institute for Mechanical and Electrical Engineering in Sofia (Bulgaria) addresses test generation for synchronous realization of Boolean-interpreted Petri nets. He proposes using composite multivalued nets, and deals with test pattern generation for a special class of finite-state machines.
System test and diagnosis
Samvel K. Shoukourian of Yerevan State University and the Star-Laboratory of the American University of Armenia and the Armenian National Academy of Sciences (Armenia) introduces a formalization to the system test problem and proposes a new design approach for system test and its application.
A. Derezinska and J. Sosnowski from Warsaw University of Technology (Poland) present an approach for distributed diagnosis of multiprocessor systems. They solve the problem of system level diagnosis using mutual tests of modules.
D.V. Speranskiy from the Institute of Applied Mathematics and Mechanics of the Ukrainian Academy of Sciences in Donetsk (Ukraine) uses testability measures of the entropy type for problems of technical diagnostics. He proposes an extension of some transmission theory approaches to testability analysis for switching circuits.
Fault models and yields
D.P. Milovanovic and V.B. Litovski from the University of Nis (Yugoslavia) search for modeling procedures and fault models for BiCMOS circuits. Simulation results analyze fault mechanisms and behavior.
Yu.V. Malyshenko of the Research Institute GALS in Vladivostok (Russia) proposes a set of new functional fault models for analog components. W. Kuzmicz, M. Niewczas, W. Pleskacz, A. Wojtasik, A. Pfitzner, and E. Piwowarska from Warsaw University of Technology (Poland) discuss issues related to verifying manufacturability of IC cell designs. They also present new CAD tools for IC yield estimation.
Fault tolerance and reliability
M.F. Karavay from the Institute of Control Sciences of the Russian Academy of Science in Moscow submitted a manuscript on the theory of symmetry in design of fault-tolerant systems. Karavay uses a system's graph theoretical representation to design a mapping that increases the system's degree of fault tolerance.
A.N. Zhirabok and O.V. Preobrazhenskaya from the Far Eastern Technical University in Vladivostok (Russia) propose a new solution for on-line testing of logical systems.
B. Medved Rogina, K. Skala, and B. Vojnovic from the Ruder Boskovic Institute in Zagreb (Croatia) propose propagation delay distribution measurements of metastability in asynchronous systems. This work studies the problem of reliability of complex microelectronic systems by investigating the conditions under which a bistable flip-flop reaches a metastable state.
Testing special structures
R.K. Latypov and Y.L. Stolov from the Kazan State University (Russia) introduce a scheme for self-testable PLAs that provide 100% single-fault detection. They present an autonomous test of AND-EXOR PLAs based on exhaustive input testing.
E. Gizdarski from the Technical University of Ruse (Bulgaria) and I. Dear from Brunel University in Uxbridge (UK) provide detailed analysis of a test algorithm for neighborhood pattern sensitivity fault detection in RAMs. They introduce a new algorithm for RAM BIST together with some structural changes to facilitate its implementation.
F. Novak, B. Hvala, and S. Klavzar from the Jozef Stefan Institute in Ljubljana (Slovenia) analyze data compression for analog signatures. This study provides conditions for analog-signal testing using the polynomial functions for data compaction.
THIS SPECIAL ISSUE is the result of the volunteer work of many dedicated colleagues. We thank all the referees and the editorial board members of IEEE Design & Test of Computers. Also, we wholeheartedly thank the authors for submitting their work and for being very understanding throughout the process. Finally, we thank the D&T editorial office for its continuous support and help in putting together this special issue.
Yervant Zorian is a distinguished member of the technical staff at AT&T Bell Laboratories in the Test and Reliability Center of Excellence, Princeton, New Jersey. His current responsibilities include research and consulting in the areas of embedded core, IC, and multichip-module self-testing. Zorian has received the ATE&I Conference Best in Test award and the AT&T Bell Laboratories' Research & Development award.Zorian received an MSc degree in computer engineering from the University of Southern California, and a PhD in electrical engineering from McGill University, Canada. He is currently associate editor-in-chief of IEEE Design & Test of Computers and serves on the editorial boards of JETTA and the Journal of Microelectronic System Integration. Zorian is vice-chair for the IEEE Computer Society Test Technology Technical Committee.
Jan Hlavicka is a professor of computer science and vice-rector for international relations at the Czech Technical University. Earlier, he worked in computer diagnostics at the Research Institute for Mathematical Machines in Prague. He cofounded the Fault-Tolerant Systems and Diagnostics Conference, which until 1989 was Eastern Europe's most important international event in the field of testing and fault tolerance of digital systems. His interests include computer architecture, fault diagnosis, and design for testability.Hlavicka graduated in electrical engineering from the Czech Technical University and received a doctor of sciences degree in computer science from the same institution.