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Issue No. 04 - Winter (1995 vol. 12)
ISSN: 0740-7475
pp: 60-67
ABSTRACT
Realistic faults must be targeted if high-quality test and diagnosis of CMOS circuits are desired. We propose a strategy to generate high-quality IDDQ test patterns for bridging faults (BFs). We used a standard ATPG for stuck-at faults that adequately adapts to target bridging faults by IDDQ testing. The methodology applies to both combinational and sequential circuits using scan-path structures. We discuss the diagnosis capability of IDDQ test sets, as well as the addition of specifically generated vectors to improve diagnosability. Results on both test and diagnosis are provided for benchmark circuits.
INDEX TERMS
Circuit test, fault diagnosis, IDDQ testing, automatic test patter generation
CITATION
Joan Figueras, Eugeni Isern, "IDDQ Test and Diagnosis of CMOS Circuits", IEEE Design & Test of Computers, vol. 12, no. , pp. 60-67, Winter 1995, doi:10.1109/MDT.1995.473314
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