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High-quality memory testing is increasingly important, especially when RAMs and ROMs are deeply embedded in bigger systems, as the techniques based on control and observation points fail. Adopting a built-in self-test scheme for deeply embedded memories seems advantageous and industrial experience at Italtel, a telecom company, confirms it. The scheme implements in hardware the test pattern generation algorithm proposed by R. Nair, S.M. Thatte, and J.A. Abraham \cite{NTAb78}, extending it to word-based memories. Area overhead, performance degradation, additional pins, and test time are minimal, whereas we guarantee high fault coverage for the significant failure modes and full testability of the BIST hardware, as the experimental results confirm.

D. Medina, P. Camurati, M. S. Reorda, P. Prinetto, S. Barbagallo and A. Burri, "Industrial BIST of Embedded RAMs," in IEEE Design & Test of Computers, vol. 12, no. , pp. 86-95, 1995.
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