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We propose a new methodology to design asynchronous circuits that is divided in two stages: abstract synthesis and logic synthesis. The first stage is carried out by refining an abstract model, based on logic predicates describing the correct input-output behavior of the circuit, into a labeled Petri net and then into a formalization of timing diagrams (the Signal Transition Graph). This refinement involves hierarchical decomposition of the initial implementation until its size can be handled by automated logic synthesis tools, as well as replacing symbolic events occurring on the input-output ports of the labeled Petri net with up and down transitions occurring on the input-output wires of a circuit implementation.
Self-timed circuits, asynchronous circuits, concurrency models, FIFO buffer, labeled Petri net, signaling expansion, Signal Transition Graphs

A. M. Koelmans, A. V. Yakovlev and L. Lavagno, "High-Level Modeling and Design of Asynchronous Interface Logic," in IEEE Design & Test of Computers, vol. 12, no. , pp. 32-40, 1995.
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